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INTEGRATED CIRCUITS
DATA SHEET
P80CL580; P83CL580 Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
Product specification Supersedes data of 1996 Oct 04 File under Integrated circuits, IC20 1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
CONTENTS 1 2 2.1 3 4 5 6 7 7.1 7.2 8 8.1 8.2 9 9.1 9.2 9.3 9.4 10 10.1 10.2 10.3 10.4 11 11.1 11.2 11.3 11.4 12 12.1 12.2 13 13.1 14 14.1 14.2 14.3 14.4 14.5 FEATURES GENERAL DESCRIPTION ROMless version: P80CL580 APPLICATIONS ORDERING INFORMATION BLOCK DIAGRAM FUNCTIONAL DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION OVERVIEW General CPU timing MEMORY ORGANIZATION Program Memory Data Memory Special Function Registers (SFRs) Addressing I/O FACILITIES Ports Port options Port 0 options SET/RESET options TIMERS/EVENT COUNTERS Timer 0 and Timer 1 Timer T2 Timer/Counter 2 Control Register (T2CON) Watchdog Timer PULSE WIDTH MODULATED OUTPUT Prescaler Frequency Control Register (PWMP) Pulse Width Register (PWM0) ANALOG-TO-DIGITAL CONVERTER (ADC) ADC Control Register (ADCON) REDUCED POWER MODES Idle mode Power-down mode Wake-up from Power-down mode Status of external pins Power Control Register (PCON) 15 15.1 15.2 15.3 15.4 16 16.1 16.2 16.3 17 17.1 17.2 17.3 18 19 19.1 19.2 20 21 22 23 24 25 26 26.1 26.2 26.3 26.4 27 28 29
P80CL580; P83CL580
I2C-BUS SERIAL I/O Serial Control Register (S1CON) Serial Status Register (S1STA) Data Shift Register (S1DAT) Address Register (S1ADR)
STANDARD SERIAL INTERFACE SIO0: UART
Multiprocessor communications Serial Port Control and Status Register (S0CON) Baud rates INTERRUPT SYSTEM External interrupts INT2 to INT8 Interrupt priority Interrupt registers OSCILLATOR CIRCUITRY RESET External reset using the RST pin Power-on-reset SPECIAL FUNCTION REGISTERS OVERVIEW INSTRUCTION SET LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS PACKAGE OUTLINES SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1997 Mar 14
2
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
1 FEATURES
P80CL580; P83CL580
* Very low current consumption: typically 4.5 mA at 2.5 V and 8 MHz * Operating ambient temperature range: -40 to +85 C. 2 GENERAL DESCRIPTION
* Full static 80C51 Central Processing Unit * 8-bit CPU, ROM, RAM, I/O in a 56-lead VSO or 64-lead QFP package * 256 bytes on-chip RAM Data Memory * 6 kbytes on-chip ROM Program Memory for P83CL580 * External memory expandable up to 128 kbytes: RAM up to 64 kbytes and ROM up to 64 kbytes * Five 8-bit ports; 40 I/O lines * Three 16-bit Timers/Event counters * On-chip oscillator suitable for RC, LC, quartz crystal or ceramic resonator * Fifteen source, fifteen vector, nested interrupt structure with two priority levels * Full duplex serial port (UART) * I2C-bus interface for serial transfer on two lines * Analog-to-digital converter (ADC) with Power-down mode; 4 input channels and 8-bit ADC * Pulse Width Modulated (PWM) output (8-bit resolution) * Watchdog Timer * Enhanced architecture with: - non-page oriented instructions - direct addressing - four 8-byte RAM register banks - stack depth limited only by available internal RAM (maximum 256 bytes) - multiply, divide, subtract and compare instructions * Reduced power consumption through Power-down and Idle modes * Wake-up via external interrupts at Port 1 * Frequency range: 0 to 12 MHz. For ADC operation minimum 250 kHz at 2.7 V * Supply voltage: 2.5 to 6.0 V 4 ORDERING INFORMATION TYPE NUMBER(1) P8xCL580HFT P8xCL580HFH Note
The P80CL580; P83CL580 (hereafter generally referred to as P8xCL580) is manufactured in an advanced CMOS technology. The P8xCL580 has the same instruction set as the 80C51, consisting of over 100 instructions: 49 one-byte, 46 two-byte, and 16 three-byte. The device operates over a wide range of supply voltages and has low power consumption; there are two software selectable modes for power reduction: Idle and Power-down. For emulation purposes, the P85CL580 (piggy-back version) with 256 bytes of RAM is recommended. This data sheet details the specific properties of the P80CL580; P83CL580. For details of the 80C51 core and the I2C-bus see "Data Handbook IC20". 2.1 ROMless version: P80CL580
The P80CL580 is the ROMless version of the P83CL580. The mask options on the P80CL580 are fixed as follows: * All ports have option `1S' (standard port, HIGH after reset), except ports P1.6 and P1.7 which have option `2S' (open-drain, HIGH after reset) * Oscillator option: Oscillator 3 * Power-on-reset option: off. 3 APPLICATIONS
The P8xCL580 is an 8-bit general purpose microcontroller especially suited for cordless telephone and mobile communication applications. The P8xCL580 also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities.
PACKAGE NAME DESCRIPTION VERSION SOT190-1 SOT319-2
VSO56 plastic very small outline package; 56 leads QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
1. `x' = 0 or 3. Refer to the Order Entry Form (OEF) for this device for the full type number, including options/program. 1997 Mar 14 3
5
INT0 T1 VDD VSS PWM0 VSSA
3 3 3 1
INT2 to INT8 7 ADC0 to ADC3 Vref(p)(A)
1997 Mar 14
INT1
T0
3
Philips Semiconductors
BLOCK DIAGRAM
XTAL1 PROGRAM MEMORY CPU 6 Kbytes ROM 256 bytes RAM
1 (1)
XTAL2 PWM ADC STADC
EA
TWO 16-BIT TIMER/ EVENT COUNTERS (T0, T1) DATA MEMORY
ALE
PSEN
80C51 core excluding ROM/RAM
P80CL580 P83CL580
8-bit internal bus
WR
3
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
4
SERIAL UART PORT 8-BIT I/O PORTS 16-BIT TIMER/ EVENT COUNTER I2C-BUS INTERFACE WATCHDOG TIMER (T3)
MBB540
RD
3
AD0 to AD7
0
A8 to A15
PARALLEL I/O PORTS & EXT. BUS
2
3
3
1
1
1
1
P0 P1 P2 P3
TXD RXD
P4
T2
T2EX
SDA
SCL
RST
EWN
0 alternative function of port 0
2 alternative function of port 2 3 alternative function of port 3
1 alternative functions of port 1
(1) Not available in the P80CL580.
P80CL580; P83CL580
Product specification
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
6 FUNCTIONAL DIAGRAM
P80CL580; P83CL580
handbook, full pagewidth
XTAL1 LOW ORDER ADDRESS AND DATA BUS
XTAL2 PORT 0 EA PSEN ALE PWM0 VSSA Vref(p)(A) PORT 1
T2 INT2 T2EX INT3 STADC INT4 INT5 INT6 INT7 INT8 SCL SDA
ADC3 ADC2 ADC1 ADC0
P80CL580 P83CL580
PORT 2
HIGH ORDER ADDRESS BUS
RXD TXD INT0 INT1 T0 T1 WR RD
PORT 4
PORT 3
RST EWN
MBB541
VSS VDD
Fig.2 Functional diagram.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
7 7.1 PINNING INFORMATION Pinning
P80CL580; P83CL580
handbook, halfpage
ADC3 ADC2 ADC1 ADC0 Vref(p)(A) VSSA P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6
1 2 3 4 5 6 7 8 9 10 11 12 13
56
VDD
55 P2.0 54 P2.1 53 P2.2 52 PSEN 51 50 ALE EA
49 P2.3 48 P2.4 47 P2.5 46 P2.6 45 P2.7 44 P0.7 43
P4.7 14
P0.6 P80CL580 P83CL580 42 RST 15 P0.5 41 P0.4 40 P0.3 39 P0.2 38 P0.1 37 P0.0 36 P3.7/RD 35 P3.6/WR 34 P3.5/T1 33 P3.4/T0 32 P3.3/INT1 31 P3.2/INT0 30 P3.1/TXD 29 P3.0/RXD
MBB542
P1.0/INT2/T2 16 P1.1/INT3/T2EX 17 P1.2/INT4/STADC 18 P1.3/INT5 P1.4/INT6 P1.5/INT7 19 20 21
P1.6/INT8/SCL 22 P1.7/SDA PWM0 23 24
EWN 25 XTAL2 26 XTAL1 27 VSS 28
Fig.3 Pin configuration for VSO56 package.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
63 Vref(p)(A)
53 PSEN
64 VSSA
62 ADC0
61 ADC1
60 ADC2
59 ADC3
57 VDD
56 P2.0
55 P2.1
54 P2.2
handbook, full pagewidth
P4.0 P4.1 n.c. P4.2 P4.3 P4.4 P4.5 P4.6 n.c.
1 2 3 4 5 6 7 8 9
52 ALE 51 EA 50 n.c. 49 P2.3 48 P2.4 47 P2.5 46 P2.6 45 P2.7 44 P0.7 43 P0.6 42 P0.5 41 P0.4 40 P0.3 39 P0.2 38 P0.1 37 P0.0 36 n.c. 35 n.c. 34 P3.7/RD 33 P3.6/WR P3.5/T1 32
MGC765
P4.7 10 RST 11 P1.0/INT2/T2 12 P1.1/INT3/T2EX 13 P1.2/INT4/STADC 14 P1.3/INT5 15 P1.4/INT6 16 n.c. 17 n.c. 18 P1.5/INT7 19 P1.6/INT8/SCL 20 P1.7/SDA 21 PWM0 22 EWN 23 XTAL2 24
P80CL580 P83CL580
XTAL1 25
VSS 26
58 n.c.
P3.0/RXD 27
P3.1/TXD 28
P3.2/INT0 29
P3.3/INT1 30
Fig.4 Pin configuration for QFP64 package.
1997 Mar 14
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P3.4/T0 31
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
7.2 Pin description
P80CL580; P83CL580
Table 1 Pin description for VSO56 (SOT190-1) and QFP64 (SOT319-2) For more extensive description of the port pins see Chapter 10 "I/O facilities". PIN SYMBOL VSO56 ADC3 to ADC0 Vref(p)(A) VSSA P4.0 to P4.7 1 to 4 5 6 7 to 14 QFP64 59 to 62 63 64 1, 2, 4 to 8, 10 4 input channels to the ADC. Positive potential of analog-to-digital conversion reference resistor. Analog part ground. Port 4: 8-bit bidirectional I/O port. (P4.0 to P4.7). Port pins that have logic 1s written to them are pulled HIGH by internal pull-ups, and in this state can be used as inputs. As inputs, Port 4 pins that are externally pulled LOW will source current (IIL, see Chapter 23) due to the internal pull-ups. Port 4 output buffers can sink/source 4 LS TTL loads. Reset: a HIGH level on this pin for two machine cycles while the oscillator is running resets the device. * Port 1: 8-bit bidirectional I/O port (P1.0 to P1.7). Same characteristics as Port 4, but note that P1.6 and P1.7 are open-drain only. * Alternative functions: - INT2 to INT8 are external interrupt inputs - STADC is the external trigger of the analog-to-digital converter - T2 and T2EX are the Timer/event counter 2 inputs - SCL and SDA are the I2C-bus clock and data lines. Pulse Width Modulation output 0. Enable Watchdog Timer: enable for Watchdog Timer and enable Power-down mode. Crystal oscillator output: output of the inverting amplifier of the oscillator. Left open when external clock is used. Crystal oscillator input: input to the inverting amplifier of the oscillator, also the input for an externally generated clock source. Ground: circuit ground potential. * Port 3: 8-bit bidirectional I/O port (P3.0 to P3.7). Same characteristics as Port 4 * Alternative functions: - RXD is the UART serial data input (asynchronous) or data input/output (synchronous) - TXD is the UART serial data output (asynchronous) or clock output (synchronous) - INT0 and INT1 are external interrupts 0 and 1 - T0 and T1 are external inputs for timers 0 and 1. DESCRIPTION
RST P1.0/INT2/T2 P1.1/INT3/T2EX P1.2/INT4/STADC P1.3/INT5 P1.4/INT6 P1.5/INT7 P1.6/INT8/SCL P1.7/SDA PWM0 EWN XTAL2 XTAL1 VSS P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
11 12 13 14 15 16 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
PIN SYMBOL VSO56 P0.0 to P0.7 37 to 44 QFP64 37 to 44
P80CL580; P83CL580
DESCRIPTION * Port 0: 8-bit open-drain bidirectional I/O port. As an open-drain output port it can sink 8 LS TTL loads. Port 0 pins that have logic 1s written to them float, and in that state will function as high impedance inputs. * Low-order addressing: Port 0 is also the multiplexed low-order address and data bus during access to external memory. The strong internal pull-ups are used while emitting logic 1s within the low order address.
P2.0 to P2.7
55 to 53, 49 to 45
56 to 54, 49 to 45
* Port 2: 8-bit bidirectional I/O port with internal pull-ups. Same characteristics as Port 4. * High-order addressing: Port 2 emits the high-order address byte during accesses to external memory that use 16-bit addresses (MOVX @DPTR). In this application it uses the strong internal pull-ups when emitting logic 1s. During accesses to external memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register.
EA
50
51
External Access. When EA is held HIGH the CPU executes out of internal Program Memory (unless the program counter exceeds 17FFH). Holding EA LOW forces the CPU to execute out of external memory regardless of the value of the Program Counter. Address Latch Enable. Output pulse for latching the low byte of the address during access to external memory. ALE is emitted at a constant rate of 16 x fosc, and may be used for external timing or clocking purposes (assuming MOVX instructions are not used). Program Store Enable. Output read strobe to external Program Memory. When executing code out of external Program Memory, PSEN is activated twice each machine cycle. However, during each access to external Data Memory two PSEN activations are skipped. Power supply.
ALE
51
52
PSEN
52
53
VDD n.c.
56 -
57
3, 9, 17, 18, Not connected. 35, 36, 50 and 58
1997 Mar 14
9
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
8 FUNCTIONAL DESCRIPTION OVERVIEW
P80CL580; P83CL580
The device has two software-selectable modes of reduced activity for power reduction: * Idle mode; freezes the CPU while allowing the derivative functions (timers, serial I/O, ADC, PWM) and interrupt system to continue functioning. * Power-down mode; saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative. In addition, two serial interfaces are provided on-chip: * A standard UART serial interface, and * A standard I2C-bus serial interface. The I2C-bus serial interface has byte-oriented master and slave functions allowing communication with the whole family of I2C-bus compatible devices. 8.2 CPU timing
This chapter gives a brief overview of the device. The detailed functional description is in the following chapters: Chapter 9 "Memory organization" Chapter 10 "I/O facilities" Chapter 11 "Timers/event counters" Chapter 12 "Pulse Width Modulated output" Chapter 13 "Analog-to-digital converter (ADC)" Chapter 14 "Reduced power modes" Chapter 15 "I2C-bus serial I/O" Chapter 16 "Standard serial interface SIO0: UART" Chapter 17 "Interrupt system" Chapter 18 "Oscillator circuitry" Chapter 19 "Reset". 8.1 General
The P8xCL580 is a stand-alone high-performance CMOS microcontroller designed for use in real-time applications such as cordless telephone and mobile communications, instrumentation, industrial control, intelligent computer peripherals and consumer products. The device provides hardware features, architectural enhancements and new instructions to function as a controller for applications requiring up to 64 kbytes of Program Memory and/or up to 64 kbytes of Data Memory. The P8xCL580 contains a 6 kbytes Program Memory (ROM; P83CL580); a static 256 bytes Data Memory (RAM); 40 I/O lines; three 16-bit timer/event counters; a fifteen-source two priority-level, nested interrupt structure and on-chip oscillator and timing circuit, 4-channel 8-bit A/D converter, Watchdog Timer and Pulse Width Modulation output.
A machine cycle consists of a sequence of 6 states. Each state lasts for two oscillator periods, thus a machine cycle takes 12 oscillator periods or 1 s if the oscillator frequency (fosc) is 12 MHz.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
9 MEMORY ORGANIZATION 9.4 Addressing
P80CL580; P83CL580
The P8xCL580 has 6 kbytes of Program Memory (ROM; P83CL580 only) plus 256 bytes of Data Memory (RAM) on board.The device has separate address spaces for Program and Data Memory (see Fig.6). Using Port latches P0 and P2, the P8xCL580 can address up to 128 kbytes of external memory. The CPU generates both read (RD) and write (WR) signals for external Data Memory accesses, and the read strobe (PSEN) for external Program Memory. 9.1 Program Memory
The P8xCL580 has five methods for addressing source operands: * Register * Direct * Register-indirect * Immediate * Base-register plus index-register-indirect. The first three methods can be used for addressing destination operands. Most instructions have a `destination/source' field that specifies the data type, addressing methods and operands involved. For operations other than MOVs, the destination operand is also a source operand.
The P83CL580 contains 6 kbytes of internal ROM. After reset the CPU begins execution at location 0000H. The lower 6 kbytes of Program Memory can be implemented in either on-chip ROM or external Program Memory. If the EA pin is tied to VDD, then Program Memory fetches from addresses 0000H to 17FFH are directed to the internal ROM. Fetches from addresses 1800H to FFFFH are directed to external ROM. Program Counter values greater than 17FFH are automatically addressed to external memory regardless of the state of the EA pin. 9.2 Data Memory
halfpage
7FH
30H 2FH bit-addressable space (bit addresses 0 to 7F)
The P8xCL580 contains 256 bytes of internal RAM and 40 Special Function Registers (SFRs). Figure 6 shows the internal Data Memory space divided into the lower 128 bytes, the upper 128 bytes, and the SFRs space. Internal RAM locations 0 to 127 are directly and indirectly addressable. Internal RAM locations 128 to 255 are only indirectly addressable. The Special Function Register locations 128 to 255 bytes are only directly addressable. 9.3 Special Function Registers (SFRs)
R7 R0 R7 R0 R7 R0 R7 R0
20H 1FH 18H 17H 10H 0FH 08H 07H 0 4 banks of 8 registers (R0 to R7)
The upper 128 bytes are the address locations of the SFRs. Figures 7 and 8 show the Special Function Registers space. The SFRs include the port latches, timers, peripheral control, serial I/O registers, etc. These registers can only be accessed by direct addressing. There are 128 directly addressable locations in the SFR address space. Bit addressable SFRs are those that end in 000B.
MLA560 - 1
Fig.5 The lower 128 bytes of internal RAM.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
Access to memory addressing is as follows: * Registers in one of the four register banks through register, direct or register-indirect * Lower 128 bytes of internal RAM through direct or register-indirect; upper 128 bytes of internal RAM through direct * Special Function Registers through direct * External Data Memory through register-indirect * Program Memory look-up tables through base-register plus index-register-indirect.
P80CL580; P83CL580
The P8xCL580 is classified as an 8-bit device since the internal ROM, RAM, Special Function Registers, Arithmetic Logic Unit and external data bus are all 8-bits wide. It performs operations on bit, nibble, byte and double-byte data types. Facilities are available for byte transfer, logic and integer arithmetic operations. Data transfer, logic and conditional branch operations can be performed directly on Boolean variables to provide excellent bit handling.
handbook, full pagewidth
64 kbytes
EXTERNAL
64 kbytes
6 kbytes
6 kbytes
6 kbytes
OVERLAPPED SPACE
INTERNAL (EA = 1)
EXTERNAL (EA = 0)
255 INTERNAL DATA RAM 127
(1) (3)
SPECIAL FUNCTION REGISTERS
(2)
0
0
PROGRAM MEMORY
INTERNAL DATA MEMORY
MGD676
EXTERNAL DATA MEMORY
(1) Accessible via indirect addressing only. (2) Accessible via direct and indirect addressing. (3) Accessible via direct addressing.
Fig.6 Memory map.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
REGISTER MNEMONIC
BIT ADDRESS
DIRECT BYTE ADDRESS (HEX)
T3 PWMP
FFH FEH FDH
PWM0 IP1 B FF F7 FE F6 FD F5 FC F4 FB F3 FA F2 F9 F1 F8 F0
FCH F8H F0H EFH EEH EDH ECH EBH EAH
IX1 IEN1 ACC S1ADR S1DAT S1STA S1CON PSW DF DE DD DC DB DA D7 D6 D5 D4 D3 D2 D9 D1 D8 D0 EF EE ED EC E7 E6 E5 E4 EB EA E3 E2 E9 E1 E8 E0
E9H E8H E0H DBH DAH D9H D8H D0H CFH CEH CDH CCH CBH CAH C9H CF CE CD CC CB CA C9 C8 C8H C5H C4H C1H C7 C6 C5 C4 C3 C2 C1 C0 C0H SFRs containing directly addressable bits
TH2 TL2 RCAP2H RCAP2L T2CON ADCH ADCON P4 IRQ1
MGC749
Fig.7 Special Function Register memory map (continued in Fig.8).
1997 Mar 14
13
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
REGISTER MNEMONIC
BIT ADDRESS
DIRECT BYTE ADDRESS (HEX)
IP0 P3 B7
BE BD BC B6 B5 B4
BB BA B3 B2
B9 B1
B8 B0
B8H B0H AFH AEH ADH ACH ABH AAH A9H
IEN0 P2 S0BUF S0CON P1 TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP P0
AF AE AD AC A7 A6 A5 A4
AB AA A3 A2
A9 A1
A8 A0
A8H A0H 99H SFRs containing directly addressable bits
9F 97
9E 96
9D 95
9C 94
9B 93
9A 92
99 91
98 90
98H 90H 8DH 8CH 8BH 8AH 89H
8F
8E
8D
8C
8B
8A
89
88
88H 87H 83H 82H 81H
87
86
85
84
83
82
81
80
80H
MLA607
Fig.8 Special Function Register memory map (continued from Fig.7).
1997 Mar 14
14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
10 I/O FACILITIES 10.1 Ports
P80CL580; P83CL580
LOW-to-HIGH transition in the port latch; Fig.9(a). Option 2 Open-drain; quasi-bidirectional I/O with n-channel open-drain output. Use as an output requires the connection of an external pull-up resistor; see Fig.9(b). Option 3 Push-pull; output with drive capability in both polarities. Under this option, pins can only be used as outputs; see Fig.9(c). 10.3 Port 0 options
The P8xCL580 has 40 I/O lines treated as one 8-bit port plus 32 individually addressable bits or as five parallel 8-bit addressable ports. Port 4 has no alternative functions. To enable a port pin alternative function for Ports 0, 1, 2 and 3, the port bit latch in its SFR must contain a logic 1. The alternative functions are detailed below: Port 0 Provides the multiplexed low-order address and data bus for expanding the device with standard memories and peripherals. Port 1 Used for a number of special functions: * Provides the inputs for the external interrupts: INT2 to INT8. * External activation of Timer 2: T2. * External trigger of the ADC: STADC. * The I2C-bus interface: SCL and SDA. Port 2 Provides the high-order address when expanding the device with external Program or Data Memory. Port 3 Pins can be configured individually to provide: * External interrupt request inputs: INT1 and INT0. * Counter input: T1 and T0. * Control signals to read and write to external memories: RD and WR. * UART input and output: RXD and TXD. Each port consists of a latch (SFRs P0 to P4), an output driver and input buffer. Ports 1, 2, 3 and 4 have internal pull-ups (except P1.6 and P1.7). Figure 9(a) shows that the strong transistor `p1' is turned on for only 2 oscillator periods after a LOW-to-HIGH transition in the port latch. When on, it turns on `p3' (a weak pull-up) through the inverter. This inverter and `p3' form a latch which holds the logic 1. In Port 0 the pull-up `p1' is only on when emitting logic 1s for external memory access. Writing a logic 1 to a Port 0 bit latch leaves both output transistors switched off so that the pin can be used as an high-impedance input. 10.2 Port options
The definition of port options for Port 0 is slightly different. Two cases are considered. First, access to external memory (EA = 0 or access above the built-in memory boundary) and second, I/O accesses. 10.3.1 EXTERNAL MEMORY ACCESSES
Option 1 True logic 0 and logic 1 are written as address to the external memory (strong pull-up to be used). Option 2 An external pull-up resistor is required for external accesses. Option 3 Not allowed for external memory accesses as the port can only be used as output. 10.3.2 I/O ACCESSES
Option 1 When writing a logic 1 to the port latch, the strong pull-up `p1' will be on for 2 oscillator periods. No weak pull-up exists. Without an external pull-up, this option can be used as a high-impedance input. Option 2 Open-drain; quasi-directional I/O with n-channel open-drain output. Use as an output requires the connection of an external pull-up resistor. See Fig.9(b). Option 3 Push-Pull; output with drive capability in both polarities. Under this option pins can only be used as outputs. See Fig.9(c). 10.4 SET/RESET options
38 of the 40 port pins (excluding P1.6 and P1.7 with option 2S only) may be individually configured with one of the following options. These options are also shown in Fig.9. Option 1 Standard Port; quasi-bidirectional I/O with pull-up. The strong booster pull-up `p1' is turned on for two oscillator periods after a 1997 Mar 14 15
Individual mask selection of the post-reset state is available with any of the above pins. The selection is made by appending `S' or `R' to Options 1, 2, or 3 above. Option R RESET, at reset this pin will be initialized LOW. Option S SET, at reset this pin will be initialized HIGH.
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
handbook, full pagewidth
strong pull-up 2 oscillator periods p1
+5 V
p2 p3 I/O pin
Q from port latch
n
input data read port pin INPUT BUFFER (a) Standard
+5 V
external pull-up Q from port latch I/O pin n
input data read port pin INPUT BUFFER
(b) Open-drain
strong pull-up +5 V
p1 I/O pin Q from port latch n
(c) Push-pull
MGD677
Fig.9 Port configuration options.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
11 TIMERS/EVENT COUNTERS The P8xCL580 contains three 16-bit timer/event counter registers; Timer 0, Timer 1 and Timer 2 which can perform the following functions: * Measure time intervals and pulse durations * Count events * Generate interrupt requests. In the `Timer' operating mode the register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 112 x fosc. In the `Counter' operating mode, the register is incremented in response to a HIGH-to-LOW transition. Since it takes 2 machine cycles (24 oscillator periods) to recognize a HIGH-to-LOW transition, the maximum count rate is 124 x fosc. To ensure a given level is sampled, it should be held for at least one complete machine cycle. 11.1 Timer 0 and Timer 1 11.2.1
P80CL580; P83CL580
CAPTURE MODE
Figure 10 shows the Capture mode. Two options in this mode, may be selected by the EXEN2 bit in T2CON: * If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter which upon overflowing sets the Timer 2 overflow bit TF2, this may then be used to generate an interrupt. * If EXEN2 = 1, Timer 2 operates as described above but with the additional feature that a HIGH-to-LOW transition at external input T2EX causes the current value in TL2 and TH2 to be captured into registers RCAP2L and RCAP2H respectively. In addition, the transition at T2EX causes the EXF2 bit in T2CON to be set; this may also be used to generate an interrupt. 11.2.2 AUTO-RELOAD MODE
Figure 11 shows the Auto-reload mode. Also two options in this mode are selected by the EXEN2 bit in T2CON: * If EXEN2 = 0, then when Timer 2 rolls over, it sets the TF2 bit but also causes the Timer 2 registers to be reloaded with the 16-bit value held in registers RCAP2L and RCAP2H. The 16-bit value held in these registers is preset by software. * If EXEN2 = 1, Timer 2 operates as described above but with the additional feature that a HIGH-to-LOW transition at external input T2EX will also trigger the 16-bit reload and set the EXF2 bit. 11.2.3 BAUD RATE GENERATOR MODE
Timer 0 and Timer 1 can be programmed independently to operate in four modes: Mode 0 8-bit timer or 8-bit counter each with divide-by-32 prescaler. Mode 1 16-bit time-interval or event counter. Mode 2 8-bit time-interval or event counter with automatic reload upon overflow. Mode 3 Timer 0 establishes TL0 and TH0 as two separate counters. 11.2 Timer T2
The Baud Rate Generator mode is selected when RTCLK = 1. It will be described in conjunction with the serial port (UART); see Section 16.3.2.
Timer T2 is a 16-bit timer/counter that can operate (like Timer 0 and 1) either as a timer or as an event counter. These functions are selected by the state of the C/T2 bit in the T2CON register; see Tables 2 and 3. Three operating modes are available Capture, Auto-reload and Baud Rate Generator, which also are selected via the T2CON register; see Table 4.
1997 Mar 14
17
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
handbook, full pagewidth
OSC
12
C/T2 = 0 TL2 (8 BITS) TH2 (8 BITS) TF2
T2 PIN
C/T2 = 1
control TR2 capture Timer 2 interrupt RCAP2L RCAP2H EXF2
MLA608
transition detector T2EX PIN control EXEN2
Fig.10 Timer 2 in Capture mode.
handbook, full pagewidth
OSC
12
C/T2 = 0 TL2 (8 BITS) TH2 (8 BITS) TF2
T2 PIN
C/T2 = 1
control TR2 reload Timer 2 interrupt RCAP2L RCAP2H
transition detector T2EX PIN control EXEN2
EXF2
MLA609
Fig.11 Timer 2 in Auto-Reload mode.
1997 Mar 14
18
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
11.3 Timer/Counter 2 Control Register (T2CON) Timer/Counter 2 Control Register (SFR address C8H) 6 EXF2 5 GF2 4 RTCLK 3 EXEN2
P80CL580; P83CL580
Table 2 7 TF2 Table 3 BIT 7 6
2 TR2
1 C/T2
0 CP/RL2
Description of T2CON bits. SYMBOL TF2 EXF2 DESCRIPTION Timer 2 overflow flag. Set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when RTCLK = 1. Timer 2 external flag. Set when either a capture or reload is caused by a negative transition on T2EX and when EXEN2 = 1. When Timer T2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to Timer 2 interrupt routine. EXF2 must be cleared by software. General purpose flag bit. Receive/transmit clock flag. When set, causes the UART serial port to use Timer 2 overflow pulses for its receive and transmit clock in Modes 1 and 3. RTCLK = 0 causes Timer 1 overflows to be used for the receive and transmit clock. Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX, if Timer 2 is not being used to clock the serial port. EXEN2 = 0, causes Timer 2 to ignore events at T2EX. Start/stop control for Timer 2. TR2 = 1 starts the timer. Timer or counter select for Timer 2. C/T2 = 0 selects the internal timer with a clock frequency of 112 x fosc. C/T2 = 1 selects the external event counter; negative edge triggered. Capture/Reload flag. When set, captures will occur on negative transitions at T2EX, if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When RTCLK = 1, this bit is ignored and the timer is forced to auto-reload on a Timer 2 overflow.
5 4
GF2 RTCLK
3
EXEN2
2 1
TR2 C/T2
0
CP/RL2
Table 4
Timer 2 operating modes; X = don't care. CP/RL2 0 1 X X TR2 1 1 1 0 16-bit Auto-reload 16-bit Capture Baud Rate Generator Off MODE
RTCLK 0 0 1 X
1997 Mar 14
19
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
11.4 Watchdog Timer
P80CL580; P83CL580
When a timer overflow occurs, the microcontroller is reset and a reset output pulse is generated at the RST pin. To prevent a system reset the timer must be reloaded in time by the application software. If the processor suffers a hardware/software malfunction, the software will fail to reload the timer. This failure will produce a reset upon overflow thus preventing the processor running out of control. The Watchdog Timer can only be reloaded if the condition flag WLE (PCON.4) has been previously set by software. At the moment the counter is loaded the condition flag is automatically cleared. The time interval between the timer reloading and the occurrence of a reset is dependent upon the reloaded value. For example, this time period may range from 2 ms to 500 ms when using an oscillator frequency fosc = 12 MHz.
In addition to Timer T2 and the standard timers, a Watchdog Timer (consisting of an 11-bit prescaler and an 8-bit timer) is also incorporated. The Watchdog Timer is controlled by the Watchdog Enable pin (EWN). When EWN = 0, the timer is enabled and the Power-down mode is disabled. When EWN = 1, the timer is disabled and the Power-down mode is enabled. In the Idle mode the Watchdog Timer and reset circuitry remain active. The Watchdog Timer is shown in Fig. 12. The timer frequency is derived from the oscillator frequency using the following formula: f osc f timer = -------------------------------( 12 x 2048 )
handbook, full pagewidth
INTERNAL BUS VDD
fosc/12
PRESCALER 11-BIT
CLEAR
TIMER T3 (8-BIT)
LOAD LOADEN
overflow
P RST
internal reset
CLEAR
write T3
R PD
LOADEN
WLE PCON.4
RST
PCON.1
EWN
INTERNAL BUS
MGD678
Fig.12 Functional diagram of the T3 Watchdog Timer.
1997 Mar 14
20
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
12 PULSE WIDTH MODULATED OUTPUT One Pulse Width Modulated output channel (PWM0) is provided which outputs pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler (PWMP) that generates the clock for the counter. The 8-bit counter counts modulo 255, i.e. from 0 to 254 inclusive. The value held in the 8-bit counter is compared to the contents of the register PWM0. Provided the contents of this register are greater than the counter value, the PWM0 output is set LOW. If the contents of register PWM0 are equal to, or less than the counter value, the PWM0 output is set HIGH. The pulse-width-ratio is therefore defined by the contents of register PWM0. The pulse-width-ratio will be in the range 0 to 255255 and may be programmed in increments of 1255. 12.1 Prescaler Frequency Control Register (PWMP) Prescaler Frequency Control Register (address FEH) 6 PWMP.6 5 PWMP.5 4 PWMP.4 3 PWMP.3
P80CL580; P83CL580
The repetition frequency (fPWM) at the PWM0 output is given by: f osc f PWM = ---------------------------------------------------------------------------{ 2 x ( 1 + PWMP ) x 255 } For fosc = 12 MHz the above formula gives a repetition frequency range of 92 Hz to 23.5 kHz. By loading the PWM0 register with either 00H or FFH, the PWM0 output can be retained at a constant HIGH or LOW level respectively. When loading FFH into the PWM0 register, the 8-bit counter will never actually reach this value. The PWM0 output pin is driven by push-pull drivers and is not shared with any other function.
Table 5 7
2 PWMP.2
1 PWMP.1
0 PWMP.0
PWMP.7 Table 6 BIT 7 to 1 12.2
Description of PWMP bits SYMBOL PWMP.7 to PWMP.0 DESCRIPTION Prescaler division factor = (PWMP) + 1.
Pulse Width Register (PWM0) Pulse Width Register (address FCH) 6 PWM0.6 5 PWM0.5 4 PWM0.4 3 PWM0.3 2 PWM0.2 1 PWM0.1 0 PWM0.0
Table 7 7
PWM0.7 Table 8 BIT 7 to 1
Description of PWM0 bits SYMBOL PWM0.7 to PWM0.0 DESCRIPTION ( PWM0 ) LOW/HIGH ratio of PWM0 signal = -------------------------------------------------{ 255 - ( PWM0 ) }
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
handbook, full pagewidth
I N T E R N A L B U S
PWM0
8-BIT COMPARATOR fosc
OUTPUT BUFFER
PWM0
1/2
PRESCALER PWMP
8-BIT COUNTER
MGC750
Fig.13 Functional diagram of Pulse Width Modulated output (PWM0).
1997 Mar 14
22
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
13 ANALOG-TO-DIGITAL CONVERTER (ADC) The analog input circuitry consists of a 4-bit analog multiplexer and an ADC with 8-bit resolution. The analog reference voltage (Vref(p)(A)) and analog ground (VSSA) are connected via separate input pins. The conversion is selectable from 24 machine cycles (24 s at fosc = 12 MHz) to 48 machine cycles. The functional diagram of the ADC is shown in Fig. 14. The ADC is controlled using the ADC Control Register (ADCON). Input channels are selected by the analog multiplexer via the ADCON register bits AADR0 and AADR1. The completion of the 8-bit ADC conversion is flagged by ADCI in the ADCON register and the result is stored in the Special Function Register ADCH (address C5H). An ADC conversion in progress is unaffected by an external software ADC start.
P80CL580; P83CL580
The result of a completed conversion remains unaffected provided ADCI = 1. While ADCS = 1 or ADCI = 1, a new ADC start will be blocked and consequently lost. An ADC conversion already in progress is aborted when the Power-down mode is entered. The result of a completed conversion (ADCI = 1) remains unaffected when entering the Idle or Power-down mode. The analog-to-digital conversion can be started in 3 ways: * Start in operating mode, continue in operating mode * Start in operating mode, by setting the ADCS bit, then go to Idle mode * Set the ADEX bit, go to the Idle mode and start conversion externally via the STADC pin. For the three cases mentioned above the internal flag ADCI is set upon completion of the conversion.
handbook, full pagewidth
STADC ADEX + Vref(p)(A)
ADC0 ADC1 ADC2 ADC3 START END VSSA 8-BIT ADC (succesive approximation)
ANALOG INPUT MULTIPLEXER
ADCON
(1)
0
1
2
3
4
5
6
-
0
1
2
3
4
5
6
7
ADCH
INTERNAL BUS
MGC751
(1) For the descriptions of ADCON bits see Table 10.
Fig.14 Functional diagram of analog input.
1997 Mar 14
23
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
13.1 ADC Control Register (ADCON) ADC Control Register (address C4H) 6 ADPD 5 ADEX 4 ADCI 3 ADCS
P80CL580; P83CL580
Table 9 7 -
2 CKDIV
1 AADR1
0 AADR0
Table 10 Description of ADCON bits BIT 7 6 5 SYMBOL - ADPD ADEX Reserved. Power-down. This bit switches off the resistor reference to save power even when the CPU is operating. Enable external start of conversion. This bit determines whether a conversion can be started using the external pin STADC. When ADEX = 0, a conversion cannot be started externally using STADC. When ADEX = 1, a conversion can be started externally using STADC. ADC interrupt flag. This flag is set when an ADC conversion result is ready to be read. An interrupt is invoked if this is enabled. This flag must be cleared by software (it cannot be set by software); see Table 11. ADC start and status flag. When this bit is set an ADC conversion is started. ADCS may be set by software or by the external signal STADC. The ADC logic ensures that this signal is HIGH while the ADC is busy. On completion of the conversion ADCS is reset and after that the interrupt flag ADCI is set. ADCS cannot be reset by software; see Table 11. This bit selects the conversion time, in terms of instruction cycles. This allows the CPU to be run at the maximum frequency (12 MHz) yet keeping the ADC timing at low frequency. When CKDIV = 0, the conversion time is equivalent to 24 instruction cycles. When CKDIV = 1, the conversion time is equivalent to 48 instruction cycles. The conversion time includes a sampling time of 6 cycles. Analog input select. These bits are used to select one of the four analog inputs; see Table 12. They only can be changed when ADCI and ADCS are both LOW. Table 12 Selection of analog input channel AADR1 AADR0 0 0 1 1 0 1 0 1 SELECTED CHANNEL AD0 AD1 AD2 AD3 DESCRIPTION
4
ADCI
3
ADCS
2
CKDIV
1 0
AADR1 AADR0
Table 11 Analog-to-digital operation ADCI ADCS 0 0 1 1 0 1 0 1 OPERATION ADC not busy; a conversion can be started. ADC busy; start of a new conversion is blocked. Conversion completed; start of a new conversion is blocked. Intermediate status for a maximum of one machine cycle before conversion is completed (ADCI = 1, ADCS = 0).
1997 Mar 14
24
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
14 REDUCED POWER MODES There are two software selectable modes of reduced activity for further power reduction: Idle and Power-down. 14.1 Idle mode 14.2
P80CL580; P83CL580
Power-down mode
Operation in Power-down mode freezes the oscillator. The internal connections which link both Idle and Power-down signals to the clock generation circuit are shown in Fig.15. Power-down mode is entered by setting the PD bit in the Power Control Register (PCON.1, see Table 14). The instruction that sets PD is the last executed prior to going into the Power-down mode. Once in the Power-down mode, the oscillator is stopped. The contents of the on-chip RAM and the SFRs are preserved. The port pins output the value held by their respective SFRs. ALE and PSEN are held LOW. In the Power-down mode, VDD may be reduced to minimize circuit power consumption. The supply voltage must not be reduced until the Power-down mode is entered, and must be restored before the hardware reset is applied which will free the oscillator. Reset should not be released until the oscillator has restarted and stabilized. 14.3 Wake-up from Power-down mode
Idle mode operation permits the interrupt, serial ports, timer blocks, PWM and ADC to continue to function while the clock to the CPU is halted. Idle mode is entered by setting the IDL bit in the Power Control Register (PCON.0, see Table 14). The instruction that sets IDL is the last instruction executed in the normal operating mode before the Idle mode is activated Once in Idle mode, the CPU status is preserved along with the Stack Pointer, Program Counter, Program Status Word and Accumulator. The RAM and all other registers maintain their data during Idle mode. The status of the external pins during Idle mode is shown in Table 13. The following functions remain active during the Idle mode: * Timer 0, Timer 1, Timer 2 and Timer 3 * UART, I2C-bus interface * External interrupt * PWM0 (reset; output = HIGH) * ADC. These functions may generate an interrupt or reset; thus ending the Idle mode. There are two ways to terminate the Idle mode: 1. Activation of any enabled interrupt will cause IDL (PCON.0) to be cleared by hardware thus terminating the Idle mode. The interrupt is serviced, and following the RETI instruction, the next instruction to be executed will be the one following the instruction that put the device in the Idle mode. The flag bits GF0 (PCON.2) and GF1 (PCON.3) may be used to determine whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When the Idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. 2. The second way of terminating the Idle mode is with an external hardware reset, or an internal reset caused by an overflow of Timer T2. Since the oscillator is still running, the hardware reset is required to be active for two machine cycles (24 oscillator periods) to complete the reset operation. Reset redefines all SFRs but does not affect the on-chip RAM. 1997 Mar 14 25
When in Power-down mode the controller can be woken-up with either the external interrupts INT2 to INT8, or a reset operation. The wake-up operation has two basic approaches as explained in Section 14.3.1; 14.3.2 and illustrated in Fig.16. 14.3.1 WAKE-UP USING INT2 TO INT8
If any of the interrupts INT2 to INT8 are enabled, the device can be woken-up from the Power-down mode with the external interrupts. To ensure that the oscillator is stable before the controller restarts, the internal clock will remain inactive for 1536 oscillator periods. This is controlled by an on-chip delay counter. 14.3.2 WAKE-UP USING RST
To wake-up the P8xCL580, the RST pin must be kept HIGH for a minimum of 24 periods. The on-chip delay counter is inactive. The user must ensure that the oscillator is stable before any operation is attempted.
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
14.4 Status of external pins
P80CL580; P83CL580
If the data is a logic 1, the port pin is held HIGH during the Power-down mode by the strong pull-up transistor `p1'; see Fig.9(a).
The status of the external pins during Idle and Power-down mode is shown in Table 13. If the Power-down mode is activated whilst accessing external Program Memory, the port data that is held in the Special Function Register P2 is restored to Port 2.
Table 13 Status of external pins during Idle and Power-down modes MODE Idle Power-down MEMORY internal external internal external 14.5 ALE 1 1 0 0 PSEN 1 1 0 0 PWM0 active active HIGH HIGH PORT 0 port data floating port data floating PORT 1 port data port data port data port data PORT 2 port data address port data port data PORT 3 port data port data port data port data PORT 4 port data port data port data port data
Power Control Register (PCON)
Idle and Power-down modes are activated by software using this SFR. PCON is not bit addressable, the reset value of PCON is 0XX00000B. Table 14 Power Control Register (address 87H) 7 SMOD 6 - 5 - 4 WLE 3 GF1 2 GF0 1 PD 0 IDL
Table 15 Description of PCON bits BIT 7 6 and 5 4 3 and 2 1 SYMBOL SMOD - WLE DESCRIPTION Double Baud rate bit. When set to a logic 1 the baud rate is doubled when the serial port SIO0 is being used in modes 1, 2 or 3. Reserved. Watchdog Load Enable. This flag must be set by software prior to loading the Watchdog Timer (T3). It is cleared when T3 is loaded. Power-down bit. Setting this bit activates the Power-down mode. This bit can only be set if input EWN is HIGH. If a logic 1 is written to both PD and IDL at the same time, PD takes precedence. Idle mode bit. Setting this bit activates the Idle mode.
GF1 and GF0 General purpose flag bits. PD
0
IDL
1997 Mar 14
26
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
handbook, full pagewidth
XTAL2
XTAL1
OSCILLATOR
interrupts serial ports timer blocks CLOCK GENERATOR CPU
P80CL580 P83CL580
PD IDL
MGL102
Fig.15 Internal clock control in Idle and Power-down modes.
handbook, full pagewidth
power-down
RST pin
external interrupt
oscillator
MGD679
delay counter 1536 periods
24 periods
Fig.16 Wake-up operation.
1997 Mar 14
27
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
15 I2C-BUS SERIAL I/O The serial port supports the twin line I2C-bus, which consists of a serial data line (SDA) and a serial clock line (SCL). These lines also function as the I/O port lines P1.7 and P1.6 respectively. The system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. The I2C-bus serial I/O has complete autonomy in byte handling and operates in 4 modes: * Master transmitter * Master receiver * Slave transmitter * Slave receiver.
P80CL580; P83CL580
These functions are controlled by the Serial Control Register S1CON. S1STA is the Status Register whose contents may also be used as a vector to various service routines. S1DAT is the Data Shift Register and S1ADR is the Slave Address Register. Slave address recognition is performed by on-chip hardware. Figure 17 is the block diagram of the I2C-bus serial I/O.
7 SLAVE ADDRESS S1ADR 7 SDA SHIFT REGISTER GC
0
0
ARBITRATION
SYNC LOGIC
SCL 7
BUS CLOCK GENERATOR 0 CONTROL REGISTER S1CON 7 STATUS REGISTER S1STA
MLB199
0
Fig.17 Block diagram of I2C-bus serial I/O.
1997 Mar 14
28
INTERNAL BUS
S1DAT
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
15.1 Serial Control Register (S1CON)
P80CL580; P83CL580
Table 16 Serial Control Register (SFR address D8H) 7 CR2 6 ENS1 5 STA 4 STO 3 SI 2 AA 1 CR1 0 CR0
Table 17 Description of S1CON bits BIT 7 6 SYMBOL CR2 ENS1 DESCRIPTION This bit along with bits CR1 (S1CON.1) and CR0 (S1CON.0) determines the serial clock frequency when SIO is in the Master mode. See Table 18. ENABLE serial I/O. When ENS1 = 0, the serial I/O is disabled. SDA and SCL outputs are in the high impedance state; P1.6 and P1.7 function as open-drain ports. When ENS1 = 1, the serial I/O is enabled. Output port latches P1.6 and P1.7 must be set to logic 1. START flag. When this bit is set in Slave mode, the SIO hardware checks the status of the I2C-bus and generates a START condition if the bus is free or after the bus becomes free. If STA is set while the SIO is in Master mode, SIO will generate a repeated START condition. STOP flag. With this bit set while in Master mode a STOP condition is generated. When a STOP condition is detected on the I2C-bus, the SIO hardware clears the STO flag. STO may also be set in Slave mode in order to recover from an error condition. In this case no STOP condition is transmitted to the I2C-bus. However, the SIO hardware behaves as if a STOP condition has been received and releases the SDA and SCL. The SIO then switches to the not addressed slave receiver mode. The STOP flag is cleared by the hardware. SIO interrupt flag. This flag is set, and an interrupt is generated, after any of the following events occur: * A start condition is generated in Master mode * Own slave address has been received during AA = 1 * The general call address has been received while GC (S1ADR.0) = 1 and AA = 1 * A data byte has been received or transmitted in Master mode (even if arbitration is lost) * A data byte has been received or transmitted as selected slave * A Stop or Start condition is received as selected slave receiver or transmitter. 2 AA Assert Acknowledge. When this bit is set, an acknowledge (low level to SDA) is returned during the acknowledge clock pulse on the SCL line when: * Own slave address is received * General call address is received; GC (S1ADR.0) = 1 * A data byte is received while the device is programmed to be a Master Receiver * A data byte is received while the device is a selected Slave Receiver. When this bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own slave address or general call address is received. 1 0 CR1 CR0 These two bits along with the CR2 (S1CON.7) bit determine the serial clock frequency when SIO is in the Master mode. See Table 18.
5
STA
4
STO
3
SI
1997 Mar 14
29
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
Table 18 Selection of the serial clock frequency SCL in a Master mode of operation CR2 0 0 0 0 1 1 1 1 15.2 CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 fosc DIVISOR 256 224 192 160 960 120 60 not allowed BIT RATE(kHz) AT fosc 3.58 MHz 14.0 16.0 18.6 22.4 3.73 29.8 59.7 - 6 MHz 23.4 26.8 31.3 37.5 6.25 50.0 100.0 - 12 MHz 46.9 53.6 62.5 75.0 12.5 100.0 - -
Serial Status Register (S1STA)
S1STA is a read-only register.The contents of this register may be used as a vector to a service routine. This optimizes the response time of the software and consequently that of the I2C-bus. The status codes for all possible modes of the I2C-bus interface are given in Tables 21 to 25. Table 19 Serial Status Register (address D9H) 7 SC4 6 SC3 5 SC2 4 SC1 3 SC0 2 0 1 0 0 0
Table 20 Description of S1STA bits BIT 3 to 7 0 to 2 SYMBOL SC4 to SC0 - 5-bit status code. These three bits are always zero. DESCRIPTION
Table 21 MST/TRX mode S1STA VALUE 08H 10H 18H 20H 28H 30H 38H A START condition has been transmitted. A repeated START condition has been transmitted. SLA and W have been transmitted, ACK has been received. SLA and W have been transmitted, ACK received. DATA of S1DAT has been transmitted, ACK received. DATA of S1DAT has been transmitted, ACK received. Arbitration lost in SLA, R/W or DATA. DESCRIPTION
1997 Mar 14
30
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
Table 22 MST/REC mode S1STA VALUE 08H 10H 38H 40H 48H 50H 58H A START condition has been transmitted. A repeated START condition has been transmitted. Arbitration lost while returning ACK. SLA and R have been transmitted, ACK received. SLA and R have been transmitted, ACK received. DATA has been received, ACK returned. DATA has been received, ACK returned. DESCRIPTION
P80CL580; P83CL580
Table 23 SLV/REC mode S1STA VALUE 60H 68H 70H 78H 80H 88H 90H 98H A0H DESCRIPTION Own SLA and W have been received, ACK returned. Arbitration lost in SLA, R/W as MST. Own SLA and W have been received, ACK returned. General CALL has been received, ACK returned. Arbitration lost in SLA, R/W as MST. General CALL has been received. Previously addressed with own SLA. DATA byte received, ACK returned. Previously addressed with own SLA. DATA byte received, ACK returned. Previously addressed with general CALL. DATA byte has been received, ACK has been returned. Previously addressed with general CALL. DATA byte has been received, ACK has been returned. A STOP condition or repeated START condition has been received while still addressed as SLV/REC or SLV/TRX.
Table 24 SLV/TRX mode S1STA VALUE A8H B0H B8H C0H C8H DESCRIPTION Own SLA and R have been received, ACK returned. Arbitration lost in SLA, R/W as MST. Own SLA and R have been received, ACK returned. DATA byte has been transmitted, ACK received. DATA byte has been transmitted, ACK received. Last DATA byte has been transmitted (AA = 0), ACK received.
Table 25 Miscellaneous. S1STA VALUE 00H F8H DESCRIPTION Bus error during MST mode or selected SLV mode, due to an erroneous START or STOP condition. No relevant state information available, SI = 0.
1997 Mar 14
31
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
Table 26 Symbols used in Tables 21 to 25 SYMBOL SLA R W ACK ACK DATA MST SLV TRX REC 15.3 7-bit slave address Read bit Write bit Acknowledgement (acknowledge bit is logic 0) No acknowledgement (acknowledge bit is logic 1) 8-bit data byte to or from I2C-bus Master Slave Transmitter Receiver Data Shift Register (S1DAT) DESCRIPTION
P80CL580; P83CL580
S1DAT contains the serial data to be transmitted or data which has just been received. The MSB (bit 7) is transmitted or received first; i.e. data shifted from right to left. Table 27 Data Shift Register (SFR address DAH) 7 S1DAT.7 15.4 6 S1DAT.6 5 S1DAT.5 4 S1DAT.4 3 S1DAT.3 2 S1DAT.2 1 S1DAT.1 0 S1DAT.0
Address Register (S1ADR)
This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receiver/transmitter. Table 28 Address Register (SFR address DBH) 7 SLA6 6 SLA5 5 SLA4 4 SLA3 3 SLA2 2 SLA1 1 SLA0 0 GC
Table 29 Description of S1ADR bits BIT 7 to 1 0 SYMBOL SLA6 to SLA0 Own slave address. GC This bit is used to determine whether the general call address is recognized. When GC = 0, the general call address is not recognized; when GC = 1, the general call address is recognized. DESCRIPTION
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
16 STANDARD SERIAL INTERFACE SIO0: UART This serial port is full duplex which means that it can transmit and receive simultaneously. It is also receive-buffered and can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte has not been read by the time the reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed via the Special Function Register S0BUF. Writing to S0BUF loads the transmit register and reading S0BUF accesses a physically separate receive register. The serial port can operate in 4 modes: Mode 0 Serial data enters and exits through RXD. TXD outputs the shift clock. Eight bits are transmitted/received (LSB first). The baud rate is fixed at 112 x fosc. See Figs 19 and 20. Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). On receive, the stop bit goes into RB8 in Special Function Register S0CON. The baud rate is variable. See Figs 21 and 22. Mode 2 11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). On transmit, the 9th data bit (TB8 in S0CON) can be assigned the value of a logic 0 or logic 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in S0CON, while the stop bit is ignored. The baud rate is programmable to either 132 or 164 x fosc. See Figs 23 and 24. Mode 3 11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. See Figs 25 and 26. In all four modes, transmission is initiated by any instruction that uses S0BUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. 16.1
P80CL580; P83CL580
Multiprocessor communications
Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th bit goes into RB8. The following bit is the stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated, but only if RB8 = 1. This feature is enabled by setting bit SM2 in S0CON. One use of this feature, in multiprocessor systems, is as follows. When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is HIGH in an address byte and LOW in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be sent. The slaves that were not being addressed leave their SM2 bits set and go on about their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
16.2 Serial Port Control and Status Register (S0CON)
P80CL580; P83CL580
The Serial Port Control and Status Register is the Special Function Register S0CON. The register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). Table 30 Serial Port Control Register (address 98H) 7 SMO 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Table 31 Description of S0CON bits BIT 7 6 5 SYMBOL SM0 SM1 SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In these modes, if SM2 = 1, then RI will not be activated if the received 9th data bit (RB8) is a logic 0. In Mode 1, if SM2 = 1, then RI will not be activated unless a valid stop bit was received. In Mode 0, SM2 should be a logic 0. Enables serial reception and is set by software to enable reception, and cleared by software to disable reception. Is the 9th data bit that will be transmitted in Modes 2 and 3. Set or cleared by software as desired. In Modes 2 and 3, is the 9th data bit received. In Mode 1, if SM2 = 0 then RB8 is the stop bit that was received. In Mode 0, RB8 is not used. The transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit time in the other modes, in any serial transmission. Must be cleared by software. The receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial transmission (except see SM2). Must be cleared by software. DESCRIPTION These bits are used to select the serial port mode; see Table 32.
4 3 2 1
REN TB8 RB8 TI
0
RI
Table 32 Selection of the serial port modes SMO 0 0 1 1 SM1 0 1 0 1 MODE Mode 0 Mode 1 Mode 2 Mode 3 DESCRIPTION Shift register 8-bit UART 9-bit UART 9-bit UART
1 32
BAUD RATE
1 12
x fosc
variable or 164 x fosc variable
1997 Mar 14
34
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
16.3 Baud rates
P80CL580; P83CL580
Timer 1 overflow rate and the value of the SMOD bit as follows: 2 Baud Rate = ---------------- x Timer 1 Overflow Rate. 32 The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either `timer' or `counter' operation in any of its 3 running modes. In most typical applications, it is configured for `timer' operation, in the Auto-reload mode (high nibble of TMOD = 0010B). In this case the baud rate is given by the formula:
SMOD f osc 2 Baud Rate = ---------------- x ------------------------------------------------------32 { 12 x ( 256 - TH1 ) } SMOD
The baud rate in Mode 0 is fixed and may be calculated as: f osc Baud Rate = -------12 The baud rate in Mode 2 depends on the value of the SMOD bit in Special Function Register PCON and may be calculated as: 2 Baud Rate = ---------------- x f osc 64 * If SMOD = 0 (value on reset), the baud rate is 164 x fosc * If SMOD = 1, the baud rate is 132 x fosc The baud rates in Modes 1 and 3 are determined by the Timer 1 or Timer 2 overflow rate. 16.3.1 USING TIMER 1 TO GENERATE BAUD RATES
SMOD
When Timer 1 is used as the Baud Rate Generator, the baud rates in Modes 1 and 3 are determined by the Table 33 Commonly used baud rates generated by Timer 1 BAUD RATE(kb/s) 1000.0(1) 375.0(3) 62.5(4) 19.2 9.6 4.8 2.4 1.2 137.5 110.0 110.0 Notes 1. Maximum in Mode 0. 2. X = don't care. 3. Maximum in Mode 2. 4. Maximum in Modes 1 and 3. fosc (MHz) 12.000 12.000 12.000 11.059 11.059 11.059 11.059 11.059 11.986 6.000 12.000 SMOD X(2) 1 1 1 0 0 0 0 0 0 0
By configuring Timer 1 to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a 16-bit software reload, very low baud rates can be achieved. Table 33 lists commonly used baud rates and how they can be obtained from Timer 1.
C/T X X 0 0 0 0 0 0 0 0 0
TIMER 1 MODE X X Mode 2 Mode 2 Mode 2 Mode 2 Mode 2 Mode 2 Mode 2 Mode 2 Mode 1
RELOAD VALUE X X FFH FDH FDH FAH F4H E8H 1DH 72H FEEBH
1997 Mar 14
35
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
16.3.2 USING TIMER 2 TO GENERATE BAUD RATES
P80CL580; P83CL580
Where (RCAP2H; RCAP2L) is the content of registers RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The Baud Rate Generator mode for Timer 2 is shown in Fig.18. This figure is only valid if RTCLK = 1. At roll-over TH2 does not set the TF2 bit in T2CON and therefore, will not generate an interrupt. Consequently, the Timer 2 interrupt does not need to be disabled when in the Baud Rate Generator mode. If EXEN2 is set, a HIGH-to-LOW transition on T2EX will set the EXF2 bit, also in T2CON, but will not cause a reload from (RCAP2H; RCAP2L) to (TH2, TL2). Therefore, in this mode T2EX may be used as an additional external interrupt. When Timer 2 is operating as a timer (TR2 = 1), in the Baud Rate Generator mode, registers TH2 and TL2 should not be accessed (read or write). Under these conditions the timer is being incremented every state time and therefore the results of a read or write may not be accurate. The registers RCAP2H and RCAP2L however, may be read but not written to. A write might overlap a reload and cause write and/or reload errors. If a write operation is required, Timer 2 or RCAP2H/RCAP2L should first be turned off by clearing the TR2 bit.
Timer 2 is selected as a Baud Rate Generator by setting the RTCLK bit in T2CON. The Baud Rate Generator mode is similar to the Auto-reload mode, in that a roll-over in TH2 causes Timer 2 registers to be reloaded with the 16-bit value held in the registers RCAP2H and RCAP2L, which are preset by software. Baud rates in Modes 1 and 3 are determined by Timer 2's overflow rate as specified below. Timer 2 Overflow Rate Baud Rate = ----------------------------------------------------------16 The Timer 2 can be configured for either `timer' or `counter' operation. In the most typical applications, it is configured for `timer' operation (C/T2 = 0). `Timer' operation is slightly different for Timer 2 when it is being used as a Baud Rate Generator. Normally, as a timer it would increment every machine cycle at a frequency of 112 x fosc. However, as a Baud Rate Generator it increments every state time at a frequency of 12 x fosc. In this case the baud rate in Modes 1 and 3 is determined as: f osc Baud Rate = ---------------------------------------------------------------------------------------------------32 x { 65536 - ( RCAP2H; RCAP2L ) }
handbook, full pagewidth
TIMER 1 overflow 2 (note: divided by 2 not by 12) 0 1 SMOD TL2 (8 BITS) T2 PIN C/T2 = 1 control TR2 RELOAD 16 UART receive/ transmit clock transition detector T2EX PIN control EXEN2 RCAP2L RCAP2H CLK TH2 (8 BITS) 1 0 RTCLK
OSC
2
C/T2 = 0
EXF2
TIMER 2 interrupt (additional external interrupt)
MGD622
Fig.18 Timer 2 in Baud Rate Generator mode.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
handbook, full pagewidth
INTERNAL BUS
write to SBUF RXD P3.0 ALT output function SHIFT
DS CL
Q
S0 BUFFER
ZERO DETECTOR
START S6 TX CLOCK
TX CONTROL
T1
SHIFT SEND
serial port interrupt SHIFT CLOCK R1
TXD P3.1 ALT output function
RX CLOCK REN RI START
RECEIVE
RX CONTROL
SHIFT 1 1 11111 0
INPUT SHIFT REGISTER SHIFT LOAD SBUF
RXD P3.0 ALT input function
S0 BUFFER
READ SBUF
INTERNAL BUS
MGC752
Fig.19 Serial port Mode 0.
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P80CL580; P83CL580
Product specification
Fig.20 Serial port Mode 0 timing.
handbook, full pagewidth
1997 Mar 14
D1 D2 D3 D4 D5 D6 D7 T R A N S M I T S6P1
Philips Semiconductors
...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6
ALE
WRITE TO SBUF
SEND
S6P2
SHIFT
RXD (DATA OUT)
D0
TSC (SHIFT CLOCK)
S3P1
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
WRITE TO SCON (CLEAR R1)
38
D0 D1 D2 D3 D4 D5 D6 D7
MLA567
RI
RECEIVE
R E C E I V E
SHIFT RXD (DATA IN)
S5P2
TXD (SHIFT CLOCK)
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
handbook, full pagewidth
INTERNAL BUS TB8
Timer 1 overflow
Timer 2 overflow
write to SBUF
2 0 SMOD RTCLK 1 0 1
DS Q CL
S0 BUFFER
TXD
ZERO DETECTOR
SHIFT
START 16 TX CLOCK
TX CONTROL
T1
SHIFT DATA SEND
serial port interrupt 16 sample HIGH-TO-LOW TRANSITION DETECTOR RX CLOCK START R1 LOAD SBUF SHIFT
RX CONTROL
BIT DETECTOR RXD LOAD SBUF
INPUT SHIFT REGISTER (9-BITS) SHIFT
S0 BUFFER
READ SBUF
INTERNAL BUS
MGC755
Fig.21 Serial port Mode 1.
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P80CL580; P83CL580
Product specification
Fig.22 Serial port Mode 1 timing.
handbook, full pagewidth
1997 Mar 14
D0 D1 D6 D2 D3 D7 D4 D5 STOP BIT T R A N S M I T /16 RESET
Philips Semiconductors
TX CLOCK
WRITE TO SBUF
SEND
DATA
S1P1
SHIFT
TXD
START BIT
TI
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
RX CLOCK START BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT
40
RXD
R E C E I V E
BIT DETECTOR SAMPLE TIME
SHIFT
RI
MLA569
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
handbook, full pagewidth
INTERNAL BUS TB8 write to SBUF
phase 2 clock (fosc / 2)
DS CL
Q
S0 BUFFER
TXD
2 0 CSMOD at PCON.7 1 SHIFT ZERO DETECTOR
STOP BIT START 16 TX CLOCK
TX CONTROL
T1
SHIFT DATA SEND
serial port interrupt 16 sample HIGH-TO-LOW TRANSITION DETECTOR RX CLOCK START R1 LOAD SBUF SHIFT
RX CONTROL
BIT DETECTOR RXD LOAD SBUF
INPUT SHIFT REGISTER (9-BITS) SHIFT
S0 BUFFER
READ SBUF
INTERNAL BUS
MGC754
Fig.23 Serial port Mode 2.
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P80CL580; P83CL580
Product specification
Fig.24 Serial port Mode 2 timing.
handbook, full pagewidth
1997 Mar 14
D0 STOP BIT D1 D2 D3 D7 TB8 D4 D5 D6 T R A N S M I T /16 RESET
Philips Semiconductors
TX CLOCK
WRITE TO SBUF
SEND
DATA
S1P1
SHIFT
TXD
START BIT
TI
STOP BIT GEN
RX CLOCK START BIT D0 D1 D2 D3 D4 D5 D6 D7 RB8 STOP BIT
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
42
RXD
R E C E I V E
BIT DETECTOR SAMPLE TIME
SHIFT
MLA571
RI
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
handbook, full pagewidth
INTERNAL BUS TB8 write to SBUF Timer 1 overflow Timer 2 overflow
DS CL
Q
S0 BUFFER
TXD
2 0 SMOD RTCLK SHIFT DATA SEND T1 serial port interrupt 16 sample HIGH-TO-LOW TRANSITION DETECTOR RX CLOCK START R1 LOAD SBUF SHIFT 1 0 1 ZERO DETECTOR SHIFT
START 16 TX CLOCK
TX CONTROL
RX CONTROL
BIT DETECTOR RXD LOAD SBUF
INPUT SHIFT REGISTER (9-BITS) SHIFT
S0 BUFFER
READ SBUF
INTERNAL BUS
MGC753
Fig.25 Serial port Mode 3.
1997 Mar 14
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P80CL580; P83CL580
Product specification
Fig.26 Serial port Mode 3 timing.
handbook, full pagewidth
1997 Mar 14
D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT T R A N S M I T /16 RESET
Philips Semiconductors
TX CLOCK
WRITE TO SBUF
DATA
SEND
S1P1
SHIFT
TXD
START BIT
TI
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
RX CLOCK START BIT D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT
44
RXD
R E C E I V E
BIT DETECTOR SAMPLE TIME
SHIFT
RI
MLA573
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
17 INTERRUPT SYSTEM External events and the real-time-driven on-chip peripherals require service by the CPU at unpredictable times. To tie the asynchronous activities of these functions to normal program execution a multiple-source, two-priority-level, nested interrupt system is provided. The system is shown in Fig.27. The P8xCL580 acknowledges interrupt requests from fifteen sources as follows: * INT0 to INT8 * Timer 0, Timer 1 and Timer 2 * I2C-bus serial I/O * UART * ADC. Each interrupt vectors to a separate location in Program Memory for its service routine. Each source can be individually enabled or disabled by corresponding bits in the Interrupt Enable Registers (IEN0 and IEN1). The priority level is selected via the Interrupt Priority Registers (IP0 and IP1). All enabled sources can be globally disabled or enabled. Figure 27 shows the interrupt system. 17.1 External interrupts INT2 to INT8 17.2
P80CL580; P83CL580
Interrupt priority
Each interrupt source can be set to either a high priority or to a low priority. If a low priority interrupt is received simultaneously with a high priority interrupt, the high priority interrupt will be dealt with first. If interrupts of the same priority are requested simultaneously, the processor will branch to the interrupt polled first, according to the sequence shown in Table 34 and in Fig.27. The `vector address' is the ROM location where the appropriate interrupt service routine starts. Table 34 Interrupt vector polling sequence SYMBOL X0 (first) S1 X5 T0 T2 X6 X1 X2 X7 T1 X3 X8 SO X4 ADC (last) VECTOR ADDRESS (HEX) 0003 002B 0053 000B 0033 005B 0013 003B 0063 001B 0043 006B 0023 004B 0073 SOURCE External 0 I2C port External 5 Timer 0 Timer 2 External 6 External 1 External 2 External 7 Timer 1 External 3 External 8 UART External 4 ADC
Port 1 lines serve an alternative purpose as seven additional interrupts INT2 to INT8. When enabled, each of these lines may wake-up the device from the Power-down mode. Using the Interrupt Polarity Register (IX1), each pin may be initialized to be either active HIGH or active LOW. IRQ1 is the Interrupt Request Flag Register. If the interrupt is enabled, each flag will be set on an interrupt request but must be cleared by software, i.e. via the interrupt software or when the interrupt is disabled. Port 1 interrupts are level sensitive. A Port 1 interrupt will be recognized when a level (HIGH or LOW depending on the Interrupt Polarity Register) on P1.n is held active for at least one machine cycle. The interrupt request is not serviced until the next machine cycle. Figure 28 shows the external interrupt system.
A low priority interrupt routine can only be interrupted by a high priority interrupt. A high priority interrupt routine cannot be interrupted.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
handbook, full pagewidth
INTERRUPT SOURCES X0
IEN0/1 REGISTERS
IP0/1
PRIORITY HIGH LOW
S1
X5
T0
T2
X1
X2
X7
T1
X3
X8
SO
X4
ADC GLOBAL ENABLE
MGD623
Fig.27 Interrupt system.
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46
INTERRUPT POLLING SEQUENCE
X6
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
handbook, full pagewidth
IX1
IEN1
IRQ1
P1.6
X8
P1.5
X7
P1.4
X6
P1.3
X5
P1.2
X4
P1.1
X3
P1.0
X2
MGD626
WAKE-UP
Fig.28 External interrupt configuration.
17.3
Interrupt registers
The registers used in the interrupt system are listed in Table 35. Tables 36 to 47 describe the contents of these registers. Table 35 Special Function Registers related to the interrupt system ADDRESS A8H E8H B8H F8H E9H C0H REGISTER IEN0 IEN1 IP0 IP1 IX1 IRQ1 Interrupt Enable Register Interrupt Enable Register (INT2 to INT8) Interrupt Priority Register Interrupt Priority Register (INT2 to INT8, ADC) Interrupt Polarity Register Interrupt Request Flag Register DESCRIPTION
1997 Mar 14
47
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
17.3.1 INTERRUPT ENABLE REGISTER (IEN0)
P80CL580; P83CL580
Bit values: 0 = interrupt disabled; 1 = interrupt enabled. Table 36 Interrupt Enable Register (SFR address A8H) 7 EA 6 ET2 5 ES1 4 ES0 3 ET1 2 EX1 1 ET0 0 EX0
Table 37 Description of IEN0 bits BIT 7 6 5 4 3 2 1 0 17.3.2 SYMBOL EA ET2 ES1 ES0 ET1 EX1 ET0 EX0 DESCRIPTION General enable/disable control. If EA = 0, no interrupt is enabled. If EA = 1, any individually enabled interrupt will be accepted. enable T2 interrupt enable I2C interrupt enable UART SIO interrupt enable Timer 1 interrupt (T1) enable external interrupt 1 enable Timer 0 interrupt (T0) enable external interrupt 0
INTERRUPT ENABLE REGISTER (IEN1)
Bit values: 0 = interrupt disabled; 1 = interrupt enabled. Table 38 Interrupt Enable Register (SFR address E8H) 7 EAD 6 EX8 5 EX7 4 EX6 3 EX5 2 EX4 1 EX3 0 EX2
Table 39 Description of IEN1 bits BIT 7 6 5 4 3 2 1 0 SYMBOL EAD EX8 EX7 EX7 EX5 EX4 EX3 EX2 Enable ADC interrupt. enable external interrupt 8 enable external interrupt 7 enable external interrupt 6 enable external interrupt 5 enable external interrupt 4 enable external interrupt 3 enable external interrupt 2 DESCRIPTION
1997 Mar 14
48
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
17.3.3 INTERRUPT PRIORITY REGISTER (IP0)
P80CL580; P83CL580
Bit values: 0 = low priority; 1 = high priority. Table 40 Interrupt Priority Register (SFR address B8H) 7 - 6 PT2 5 PS1 4 PS0 3 PT1 2 PX1 1 PT0 0 PX0
Table 41 Description of IP0 bits BIT 7 6 5 4 3 2 1 0 17.3.4 SYMBOL - PT2 PS1 PS0 PT1 PX1 PT0 PX0 reserved Timer 2 interrupt priority level I2C interrupt priority level UART SIO interrupt priority level Timer 1 interrupt priority level external interrupt 1 priority level Timer 0 interrupt priority level external interrupt 0 priority level DESCRIPTION
INTERRUPT PRIORITY REGISTER (IP1)
Bit values: 0 = low priority; 1 = high priority. Table 42 Interrupt Priority Register (SFR address F8H) 7 PADC 6 PX8 5 PX7 4 PX6 3 PX5 2 PX4 1 PX3 0 PX2
Table 43 Description of IP1 bits BIT 7 6 5 4 3 2 1 0 SYMBOL PADC PX8 PX7 PX6 PX5 PX4 PX3 PX2 ADC interrupt priority level external interrupt 8 priority level external interrupt 7 priority level external interrupt 6 priority level external interrupt 5 priority level external interrupt 4 priority level external interrupt 3 priority level external interrupt 2 priority level DESCRIPTION
1997 Mar 14
49
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
17.3.5 INTERRUPT POLARITY REGISTER (IX1)
P80CL580; P83CL580
Writing either a logic 1 or logic 0 to any Interrupt Polarity Register bit sets the polarity level of the corresponding external interrupt to an active HIGH or active LOW respectively. Table 44 Interrupt Polarity Register (SFR address E9H) 7 - 6 IL8 5 IL7 4 IL6 3 IL5 2 IL4 1 IL3 0 IL2
Table 45 Description of IX1 bits BIT 7 6 5 4 3 2 1 0 17.3.6 SYMBOL - IL8 IL7 IL6 IL5 IL4 IL3 IL2 reserved external interrupt 8 polarity level external interrupt 7 polarity level external interrupt 6 polarity level external interrupt 5 polarity level external interrupt 4 polarity level external interrupt 3 polarity level external interrupt 2 polarity level DESCRIPTION
INTERRUPT REQUEST FLAG REGISTER (IRQ1)
Table 46 Interrupt Request Flag Register (SFR address C0H) 7 - 6 IQ8 5 IQ7 4 IQ6 3 IQ5 2 IQ4 1 IQ3 0 IQ2
Table 47 Description of IRQ1 bits BIT 7 6 5 4 3 2 1 0 SYMBOL - IQ8 IQ7 IQ6 IQ5 IQ4 IQ3 IQ2 reserved external interrupt 8 request flag external interrupt 7 request flag external interrupt 6 request flag external interrupt 5 request flag external interrupt 4 request flag external interrupt 3 request flag external interrupt 2 request flag DESCRIPTION
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
18 OSCILLATOR CIRCUITRY The on-chip oscillator circuitry of the P8xCL580 is a single-stage inverting amplifier biased by an internal feedback resistor. The oscillator circuit is shown in Fig.30. For operation as a standard quartz oscillator, no external components are needed, except for the 32 kHz option. When using external capacitors, ceramic resonators, coils and RC networks to drive the oscillator, five different configurations are supported (see Table 48 and Fig.29). In the Power-down mode the oscillator is stopped and XTAL1 is pulled HIGH. The oscillator invertor is switched off to ensure no current will flow regardless of the voltage at XTAL1, for configurations (a), (b), (c), (d), (e) and (g) of Fig.29. Table 48 Oscillator options OPTION Oscillator 1 Oscillator 2 Oscillator 3 Oscillator 4 RC oscillator APPLICATION
P80CL580; P83CL580
To drive the device with an external clock source, apply the external clock signal to XTAL1, and leave XTAL2 to float, as shown in Fig.29(f). There are no requirements on the duty cycle of the external clock, since the input to the internal clocking circuitry is buffered by a flip-flop. Various oscillator options are provided for optimum on-chip oscillator performance; these are specified in Table 48 and shown in Fig.29. The required option should be stated when ordering.
For 32 kHz clock applications with external trimmer for frequency adjustment. A 4.7 M bias resistor is needed for use in parallel with the crystal; see Fig.29(c). Low-power, low-frequency operations using LC components; see Fig.29(e). Medium frequency range applications. High frequency range applications. RC oscillator configuration; see Figs 29(g) and 31.
handbook, full pagewidth
STANDARD QUARTZ OSCILLATOR XTAL1 XTAL2
QUARTZ OSCILLATOR WITH EXTERNAL CAPACITORS
32 kHz OSCILLATOR XTAL1 XTAL2
XTAL1
XTAL2
(a)
(b)
(c)
CERAMIC RESONATOR XTAL1 XTAL2
LC - OSCILLATOR XTAL1 XTAL2
EXTERNAL CLOCK XTAL1 XTAL2 n.c.
RC - OSCILLATOR XTAL1 n.c. VDD XTAL2
(d)
(e)
(f)
(g)
MLA577
Fig.29 Oscillator configurations.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
VDD
P80CL580 P83CL580
VDD PD
to internal timing circuits
VDD
C1 i
R bias
C2 i
XTAL1
XTAL2
MGC756
Fig.30 Standard oscillator.
MLA579
handbook, halfpage
600
f osc (kHz)
400
200
0 0 2 4 RC (s) 6
RC oscillator frequency is externally adjustable; 100 kHz fosc 500 kHz.
Fig.31 RC oscillator; frequency as a function of RC.
1997 Mar 14
52
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
Table 49 Oscillator type selection guide RESONATOR Quartz FREQUENCY (MHz) 0.032 1.0 3.58 4.0 6.0 10.0 12.0 16.0 PXE 0.455 1.0 3.58 4.0 6.0 10.0 12.0 LC Oscillator 3 Oscillator 4 Oscillator 2 Oscillator 2 Oscillator 4 Oscillator 3 Oscillator 2 OPTION (see Table 48) Oscillator 1 C1 EXT. (pF) MIN. 0 0 0 0 0 0 0 0 40 15 0 0 0 0 10 20 MAX. 0 30 15 20 10 15 10 15 50 50 40 40 20 15 40 90
P80CL580; P83CL580
C2 EXT. (pF) MIN. 5 0 0 0 0 0 0 0 40 15 0 0 0 0 10 20 MAX. 15 30 15 20 10 15 10 15 50 50 40 40 20 15 40 90
RESONATOR MAX. SERIES RESISTANCE 15 k; note 1 600 100 75 60 60 40 20 10 100 10 10 5 6 6 10 H = 1 100 H = 5 1 mH = 75
Note 1. 32 kHz quartz crystals with a series resistance >15 k will reduce the guaranteed supply voltage range to 2.5 to 3.5 V.
1997 Mar 14
53
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
Rf
handbook, full pagewidth
XTAL1 C1 i V1 gm R2 C2 i
XTAL2
MLA578
Fig.32 Oscillator equivalent circuit diagram.
Table 50 Oscillator equivalent circuit parameters The equivalent circuit data of the internal oscillator compares with that of matched crystals. SYMBOL gm PARAMETER transconductance OPTION Oscillator 1; 32 kHz Oscillator 2 Oscillator 3 Oscillator 4 C1i input capacitance Oscillator 1; 32 kHz Oscillator 2 Oscillator 3 Oscillator 4 C2i output capacitance Oscillator 1; 32 kHz Oscillator 2 Oscillator 3 Oscillator 4 R2 output resistance Oscillator 1; 32 kHz Oscillator 2 Oscillator 3 Oscillator 4 CONDITION Tamb = +25 C; VDD = 4.5 V - 200 400 1000 - - - - - - - - - - - - MIN. TYP. 15 600 1 500 4000 3.0 8.0 8.0 8.0 23 8.0 8.0 8.0 3800 65 18 5.0 MAX. - 1000 4000 10000 - - - - - - - - - - - - UNIT S S S S pF pF pF pF pF pF pF pF k k k k
1997 Mar 14
54
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
19 RESET To initialize the P8xCL580 a reset is performed by either of three methods: * Applying an external signal to the RST pin * Via Power-on-reset circuitry * Watchdog Timer. A reset leaves the internal registers as shown in Chapter 20. The reset state of the port pins is mask-programmable and can be defined by the user. 19.1 External reset using the RST pin 19.2
P80CL580; P83CL580
Power-on-reset
The device contains on-chip circuitry which switches the port pins to the customer defined logic level as soon as VDD exceeds 1.3 V; if the mask option `ON' has been chosen. As soon as the minimum supply voltage is reached, the oscillator will start up. However, to ensure that the oscillator is stable before the controller starts, the clock signals are gated away from the CPU for a further 1536 oscillator periods. During that time the CPU is held in a reset state. A hysteresis of approximately 50 mV at a typical power-on switching level of 1.3 V will ensure correct operation (see Fig.35). The on-chip Power-on reset circuitry can also be switched off via the mask option `OFF'. This option reduces the Power-down current to typically 800 nA and can be chosen if external reset circuitry is used. For applications not requiring the internal reset, option `OFF' should be chosen. An automatic reset can be obtained by connecting the RST pin to VDD via a 10 F capacitor. At power-on, the voltage on the RST pin is equal to VDD minus the capacitor voltage, and decreases from VDD as the capacitor charges through the internal resistor (RRST) to ground. The larger the capacitor, the more slowly VRST decreases. VRST must remain above the lower threshold of the Schmitt trigger long enough to effect a complete reset. The time required is the oscillator start-up time, plus 2 machine cycles. The Power-on-reset circuitry is shown in Fig.34.
The reset input for the P8xCL580 is RST. A Schmitt trigger is used at the input for noise rejection. The output of the Schmitt trigger is sampled by the reset circuitry every machine cycle. A reset is accomplished by holding the RST pin HIGH for at least two machine cycles (24 oscillator periods) while the oscillator is running. The CPU responds by executing an internal reset. Port pins adopt their reset state immediately after the RST goes HIGH. During reset, ALE and PSEN are held HIGH. The external reset is asynchronous to the internal clock. The RST pin is sampled during state 5, phase 2 of every machine cycle. After a HIGH is detected at the RST pin, an internal reset is repeated until RST goes LOW. The reset circuitry is also affected by the Watchdog timer; see Section 11.4. The internal RAM is not affected by reset. When VDD is turned on, the RAM contents are indeterminate.
handbook, halfpageVDD
DD handbook, halfpage
T3 overflow
V
P
10 F
P80CL580 P83CL580
RST RRST SCHMITT TRIGGER POR
MGC757
V
DD
RESET CIRCUITRY
RST R
RST
MGC760
Fig.33 Reset configuration.
Fig.34 Recommended Power-on-reset circuitry.
1997 Mar 14
55
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
switching level POR
handbook, full pagewidth SUPPLY
VOLTAGE
hysteresis
POWER-ON-RESET (INTERNAL)
OSCILLATOR
CPU RUNNING
MLA581
Start-up time
1536 oscillator periods delay
Fig.35 Power-on-reset switching level.
1997 Mar 14
56
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
20 SPECIAL FUNCTION REGISTERS OVERVIEW The P8xCL580 has 40 SFRs available to the user. ADDRESS (HEX) FF FE FC F8 F0 E9 E8 E0 DB DA D9 D8 D0 CD CC CB CA C8 C5 C4 C1 C0 T3 PWMP PWM0 IP1 B(1) IX1 IEN1(1) ACC(1) S1ADR S1DAT S1STA S1CON(1) PSW(1) TH2 TL2 RCAP2H RCAP2L T2CON(1) ADCH ADCON P4 IRQ1(1) NAME RESET VALUE (B) 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 X0000000 XXXXXXXX(2) 00000000 Watchdog Timer
P80CL580; P83CL580
FUNCTION
Prescaler Frequency Control Register Pulse Width Register 0 Interrupt Priority Register (INT2 to INT8, ADC) B Register Interrupt Polarity Register Interrupt Enable Register 1 Accumulator I2C-bus Slave Address Register I2C-bus Data Shift Register I2C-bus Serial Status Register I2C-bus Serial Control Register Program Status Word Timer 2 High byte Timer 2 Low byte Timer 2 Reload/Capture Register High byte Timer 2 Reload/Capture Register Low byte Timer/Counter 2 Control Register ADC Result Register ADC Control Register Digital I/O Port Register 4 Interrupt Request Flag Register
1997 Mar 14
57
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
ADDRESS (HEX) B8 B0 A8 A0 99 98 90 8D 8C 8B 8A 89 88 87 83 82 81 80 Notes 1. Bit addressable register. 2. Port reset state determined by the customer. NAME IP0(1) P3(1) IEN0(1) P2(1) S0BUF S0CON(1) P1(1) TH1 TH0 TL1 TL0 TMOD TCON(1) PCON DPH DPL SP P0(1) RESET VALUE (B) X0000000 XXXXXXXX(2) 00000000 XXXXXXXX(2) XXXXXXXX 00000000 XXXXXXXX(2) 00000000 00000000 00000000 00000000 00000000 00000000 0XX00000 00000000 00000000 00000111 XXXXXXXX(2) Interrupt Priority Register 0 Digital I/O Port Register 3 Interrupt Enable Register Digital I/O Port Register 2 Serial Data Buffer Register 0 Serial Port Control Register 0 Digital I/O Port Register 1 Timer 1 High byte Timer 0 High byte Timer 1 Low byte Timer 0 Low byte
P80CL580; P83CL580
FUNCTION
Timer 0 and 1 Mode Control Register Timer 0 and 1 Control/External Interrupt Control Register Power Control Register Data Pointer High byte Data Pointer Low byte Stack Pointer Digital I/O Port Register 0
1997 Mar 14
58
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
21 INSTRUCTION SET
P80CL580; P83CL580
The P8xCL580 uses a powerful instruction set which permits the expansion of on-chip CPU peripherals and optimizes byte efficiency and execution speed. Assigned opcodes add new high-power operation and permit new addressing modes. The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 12 MHz oscillator, 64 instructions execute in 1 s and 45 instructions execute in 2 s. Multiply and divide instructions execute in 4 s. For the description of the Data Addressing modes and Hexadecimal opcode cross-reference see Table 55. Table 51 Instruction set description: Arithmetic operations MNEMONIC Arithmetic operations ADD ADD ADD ADD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV DA A,Rr A,direct A,@Ri A,#data A,Rr A,direct A,@Ri A,#data A,Rr A,direct A,@Ri A,#data A Rr direct @Ri A Rr direct @Ri DPTR AB AB A Add register to A Add direct byte to A Add indirect RAM to A Add immediate data to A Add register to A with carry flag Add direct byte to A with carry flag Add indirect RAM to A with carry flag Add immediate data to A with carry flag Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate data from A with borrow Increment A Increment register Increment direct byte Increment indirect RAM Decrement A Decrement register Decrement direct byte Decrement indirect RAM Increment data pointer Multiply A and B Divide A by B Decimal adjust A 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 2* 25 26, 27 24 3* 35 36, 37 34 9* 95 96, 97 94 04 0* 05 06, 07 14 1* 15 16, 17 A3 A4 84 D4 DESCRIPTION BYTES CYCLES OPCODE (HEX)
1997 Mar 14
59
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
Table 52 Instruction set description: Logic operations MNEMONIC Logic operations ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR RRC SWAP A,Rr A,direct A,@Ri A,#data direct,A direct,#data A,Rr A,direct A,@Ri A,#data direct,A direct,#data A,Rr A,direct A,@Ri A,#data direct,A direct,#data A A A A A A A AND register to A AND direct byte to A AND indirect RAM to A AND immediate data to A AND A to direct byte AND immediate data to direct byte OR register to A OR direct byte to A OR indirect RAM to A OR immediate data to A OR A to direct byte OR immediate data to direct byte Exclusive-OR register to A Exclusive-OR direct byte to A Exclusive-OR indirect RAM to A Exclusive-OR immediate data to A Exclusive-OR A to direct byte Exclusive-OR immediate data to direct byte Clear A Complement A Rotate A left Rotate A left through the carry flag Rotate A right Rotate A right through the carry flag Swap nibbles within A DESCRIPTION
P80CL580; P83CL580
BYTES
CYCLES
OPCODE (HEX)
1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1
1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1
5* 55 56, 57 54 52 53 4* 45 46, 47 44 42 43 6* 65 66, 67 64 62 63 E4 F4 23 33 03 13 C4
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60
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
Table 53 Instruction set description: Data transfer MNEMONIC Data transfer MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVC MOVC MOVX MOVX MOVX MOVX PUSH POP XCH XCH XCH XCHD Note 1. MOV A,ACC is not permitted. A,Rr A,@Ri A,#data Rr,A Rr,direct Rr,#data direct,A direct,Rr direct,direct direct,@Ri direct,#data @Ri,A @Ri,direct @Ri,#data A,@A+DPTR A,@A+PC A,@Ri A,@DPTR @Ri,A @DPTR,A direct direct A,Rr A,direct A,@Ri A,@Ri Move register to A Move indirect RAM to A Move immediate data to A Move A to register Move direct byte to register Move immediate data to register Move A to direct byte Move register to direct byte Move direct byte to direct Move indirect RAM to direct byte Move immediate data to direct byte Move A to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Move code byte relative to DPTR to A Move code byte relative to PC to A Move external RAM (8-bit address) to A Move external RAM (16-bit address) to A Move A to external RAM (8-bit address) Move A to external RAM (16-bit address) Push direct byte onto stack Pop direct byte from stack Exchange register with A Exchange direct byte with A Exchange indirect RAM with A Exchange LOW-order digit indirect RAM with A DESCRIPTION
P80CL580; P83CL580
BYTES
CYCLES
OPCODE (HEX)
1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1
1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1
E* E5 E6, E7 74 F* A* 7* F5 8* 85 86, 87 75 F6, F7 A6, A7 76, 77 90 93 83 E2, E3 E0 F2, F3 F0 C0 D0 C* C5 C6, C7 D6, D7
A,direct (note 1) Move direct byte to A
DPTR,#data 16 Load data pointer with a 16-bit constant
1997 Mar 14
61
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
Table 54 Instruction set description: Boolean variable manipulation, Program and machine control MNEMONIC Boolean variable manipulation CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV C bit C bit C bit C,bit C,/bit C,bit C,/bit C,bit bit,C Clear carry flag Clear direct bit Set carry flag Set direct bit Complement carry flag Complement direct bit AND direct bit to carry flag AND complement of direct bit to carry flag OR direct bit to carry flag OR complement of direct bit to carry flag Move direct bit to carry flag Move carry flag to direct bit 1 2 1 2 1 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 1 2 C3 C2 D3 D2 B3 B2 82 B0 72 A0 A2 92 *1 12 22 32 1 02 80 73 60 70 40 50 20 30 10 B5 B4 B* B6, B7 D* D5 00 DESCRIPTION BYTES CYCLES OPCODE (HEX)
Program and machine control ACALL LCALL RET RETI AJMP LJMP SJMP JMP JZ JNZ JC JNC JB JNB JBC CJNE CJNE CJNE CJNE DJNZ DJNZ NOP addr11 addr16 rel @A+DPTR rel rel rel rel bit,rel bit,rel bit,rel A,direct,rel A,#data,rel Rr,#data,rel Rr,rel direct,rel addr11 addr16 Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to the DPTR Jump if A is zero Jump if A is not zero Jump if carry flag is set Jump if carry flag is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Compare direct to A and jump if not equal Compare immediate to A and jump if not equal Compare immediate to register and jump if not equal Decrement register and jump if not zero Decrement direct and jump if not zero No operation 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3 3 3 2 3 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1
@Ri,#data,rel Compare immediate to indirect and jump if not equal
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62
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
Table 55 Description of the mnemonics in the Instruction set MNEMONIC Data addressing modes Rr direct @Ri #data #data 16 bit addr16 addr11 rel Working register R0-R7. DESCRIPTION
P80CL580; P83CL580
128 internal RAM locations and any special function register (SFR). Indirect internal RAM location addressed by register R0 or R1 of the actual register bank. 8-bit constant included in instruction. 16-bit constant included as bytes 2 and 3 of instruction. Direct addressed bit in internal RAM or SFR. 16-bit destination address. Used by LCALL and LJMP. The branch will be anywhere within the 64 kbytes Program Memory address space. 111-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes page of Program Memory as the first byte of the following instruction. Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction.
Hexadecimal opcode cross-reference * * 8, 9, A, B, C, D, E, F. 1, 3, 5, 7, 9, B, D, F. 0, 2, 4, 6, 8, A, C, E.
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Table 56 Instruction map Second hexadecimal character of opcode 6 INC @Ri 0 DEC @Ri 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPL A MOV direct,A 0 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 1 0 7 7 8 F
First hexadecimal character of opcode
1997 Mar 14 3 RR A RRC A RL A RLC A 4 INC A DEC A ADD A,#data ADDC A,#data 5 INC direct DEC direct ADD A,direct ADDC A,direct
0
0
NOP
Philips Semiconductors
1
2 LJMP addr16 LCALL addr16
2
RET
3
JBC bit,rel JB bit,rel JNB bit,rel
1 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11
RETI
4
5
6
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
7
64 CJNE A,direct,rel XCH A,direct DJNZ direct,rel MOV A,direct (1)
8
9
ORL A,direct ANL A,direct XRL A,direct MOV direct,#data MOV direct,direct SUBB A,direct
A
B
C
D
E
JC rel JNC rel JZ rel JNZ rel SJMP rel MOV DTPR,#data16 ORL C,/bit ANL C,/bit PUSH direct POP direct MOVX A,@DTPR
AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11
ORL A,#data ANL A,#data XRL A,#data MOV A,#data DIV AB SUBB A,#data MUL AB CJNE A,#data,rel SWAP A DA A CLR A
F
MOVX @DTPR,A
ACALL addr11
ORL ORL direct,A direct,#data ANL ANL direct,A direct,#data XRL XRL direct,A direct,#data ORL JMP C,bit @A+DPTR ANL MOVC C,bit A,@A+PC MOV MOVC bit,C A,@A+DPTR MOV INC bit,C DPTR CPL CPL bit C CLR CLR bit C SETB SETB bit C MOVX A,@Ri 0 1 MOVX @Ri,A 0 1
0 1 ADD A,@Ri 0 1 ADDC A,@Ri 0 1 ORL A,@Ri 0 1 ANL A,@Ri 0 1 XRL A,@Ri 0 1 MOV @Ri,#data 0 1 MOV direct,@Ri 0 1 SUBB A,@Ri 0 1 MOV @Ri,direct 0 1 CJNE @Ri,#data,rel 0 1 XCH A,@Ri 0 1 XCHD A,@Ri 0 1 MOV A,@Ri 0 1 MOV @Ri,A 0 1
9ABCDE INC Rr 123456 DEC Rr 123456 ADD A,Rr 123456 ADDC A,Rr 123456 ORL A,Rr 123456 ANL A,Rr 123456 XRL A,Rr 123456 MOV Rr,#data 123456 MOV direct,Rr 123456 SUB A,Rr 123456 MOV Rr,direct 123456 CJNE Rr,#data,rel 123456 XCH A,Rr 123456 DJNZ Rr,rel 123456 MOV A,Rr 123456 MOV Rr,A 123456
P80CL580; P83CL580
Note
Product specification
1. MOV A, ACC is not a valid instruction.
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
22 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI II IO Ptot Tstg Tamb Tj supply voltage input voltage on any pin with respect to ground (VSS) DC current on any input DC current on any output total power dissipation storage temperature operating ambient temperature operating junction temperature PARAMETER
P80CL580; P83CL580
MIN. -0.5 -0.5 -5.0 -5.0 - -65 -40 -
MAX. +6.5 +5.0 +5.0 300 +150 +85 +125 V VDD + 0.5 V
UNIT
mA mA mW C C C
23 DC CHARACTERISTICS VDD = 1.8 to 6 V; VSS = 0 V; Tamb = -25 to +55 C; see notes 1 and 2; all voltages with respect to VSS unless specified. SYMBOL Supply VDD supply voltage operating RAM retention voltage in Power-down mode IDD IDD(idle) IDD(pd) VIL VIH ILI Outputs IOL LOW level output current (except SDA; SCL) VDD = 5 V; VOL = 0.4 V VDD = 2.5 V; VOL = 0.4 V VDD = 5 V; VOL = 0.4 V VDD = 2.5 V; VOL = 0.4 V IOH IOH HIGH level output current PWM0 HIGH level output current (push-pull options only) VDD = 5 V; VOH = VDD - 0.4 V VDD = 2.5 V; VOH = VDD - 0.4 V VDD = 5 V; VOH = VDD - 0.4 V VDD = 2.5 V; VOH = VDD - 0.4 V 1.6 0.7 3.0 3.2 1.6 -3.2 -1.6 -1.6 -0.7 - - - - - - - - - - - - - - - - - - mA mA mA mA mA mA mA mA mA supply current operating supply current Idle mode Power-down current VDD = 5 V; fCLK = 12 MHz; note 3 VDD = 5 V; fCLK = 12 MHz; note 4 VDD = 1.8 V; Tamb = 25C; note 5 2.5 1.0 - - - - - - - - - - - - 6.0 6.0 27.0 5.0 10.0 3.0 10 V V mA mA mA mA A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VDD = 3 V; fCLK = 3.58 MHz; note 3 - VDD = 3 V; fCLK = 3.58 MHz; note 4 - Inputs (note 6) LOW level input voltage HIGH level input voltage input leakage current (Port 0; EA) VSS < VI < VDD VSS -
0.3VDD V VDD 10 V A
0.7VDD -
LOW level output current SDA; SCL VDD = 5 V; VOL = 0.4 V LOW level output current PWM0
1997 Mar 14
65
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
SYMBOL IIL IITL RRST VIN(A) Vref(p)(A) Rref CAIN Ae OSe DLe Mctc PARAMETER input current logic 0 input current logic 0; HIGH-to-LOW transition RST pull-down resistor CONDITIONS VDD = 5 V; VIN = 0.4 V VDD = 2.5 V; VIN = 0.4 V VDD = 5 V; VIN = 0.5VDD VDD = 2.5 V; VIN = 0.5VDD
P80CL580; P83CL580
MIN. - - - - 10
TYP. - - - - - - - - 3 - - - -
MAX. -100 -50 -1.0 -500 200
UNIT A A mA A k
Analog inputs (note 7) analog input voltage reference voltage resistance between Vref(p)(A) and VSSA analog on-chip input capacitance absolute error (note 8) zero-offset error (note 9) differential non-linearity (note 10) channel-to-channel matching (note 11) VSSA 2.7 25 - - - - - VDD VDD 100 - 1 1 1 1
2
mA mA k pF LSB LSB LSB LSB
Notes to the DC characteristics 1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the LOW level output voltage of ALE, Port 1 and Port 3 pins when these make a HIGH-to-LOW transition during bus operations. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make HIGH-to-LOW transitions during bus operations. In the most adverse conditions (capacitive loading > 100 pF), the noise pulse on the ALE line may exceed 0.8 V. In such events it may be required to qualify ALE with a Schmitt trigger, or use an address latch with a Schmitt trigger strobe input. 2. Capacitive loading on Ports 0 and 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address bits are stabilizing. 3. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS; VIH = VDD; XTAL2 not connected; EA = RST = Port 0 = VDD. 4. The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS; VIH = VDD; XTAL2 not connected; EA = Port 0 = VDD. 5. The power-down current is measured with all output pins disconnected; XTAL1 not connected; EA = Port 0 = VDD; RST = VSS. 6. The input threshold voltage of P1.6/SCL and P1.7/SDA meet the I2C-bus specification. Therefore, an input voltage below 0.3VDD will be recognized as a logic 0 and an input voltage above 0.7VDD will be recognized as a logic 1. 7. VDD = 2.7 to 6 V; VSS = 0 V; VSSA = 0 V; Vref(p)(A) = VDD; Tamb = -40 to +85 C, unless otherwise specified. fxtal(min) = 250 kHz. 8. Absolute error: the maximum difference between actual and ideal code transitions. Absolute error accounts for all deviations of an actual converter from an ideal converter. 9. Zero-offset error: the difference between the actual and ideal input voltage corresponding to the first actual code transition. 10. Differential non-linearity: the difference between the actual and ideal code widths. 11. Channel-to-channel matching: the difference between corresponding code transitions of actual characteristics taken from different channels under the same temperature, voltage and frequency conditions. Not tested, but verified on sampling basis.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
fXTAL 18 (MHz) 16 14 12 10 8 6 4 2
250 kHz (1)
MGC761
24 I DD (mA) 18 12 MHz
MGC762
12
8.0 MHz
6
3.58 MHz
0 0 2
2.7 V (1)
4
VDD (V)
6
0 0 2 4 VDD (V) 6
Tamb = 25 C. Oscillator option = Oscillator 3. (1) The area above the dotted lines give the ADC operating area.
Fig.36 Frequency operating range.
Fig.37 Typical operating current as a function of frequency and VDD.
handbook, halfpage
8
MGC763
MGC764
6 handbook, halfpage IDD(pd) (A) 12 MHz 4 8.0 MHz
IDD(idle) (mA) 6
4
2 2 3.58 MHz
0 0 2 4 VDD (V) 6
0 0 2 4 V DD (V) 6
Tamb = 25 C. Oscillator option = Oscillator 3.
Tamb = 25 C.
Fig.38 Typical Idle current as a function of frequency and VDD.
Fig.39 Typical Power-down current as a function of VDD.
1997 Mar 14
67
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
handbook, full pagewidth
255 254 253 252 251 250
(2)
(4)
code out (1)
5 4 3 2 1 0
(3) 1 LSB (ideal)
1 2 3 4 5 6 7 250 251 252 253 254 255
zero offset error
VIN(A)(LSBideal)
MGD625
Vref ( p )(A) - V SSA 1LSB = ------------------------------------------ 256
(1) (2) (3) (4)
Example of an actual transfer curve. The ideal transfer curve. Differential non-linearity (DLe). Absolute error.
Fig.40 Analog-to-digital conversion characteristics.
1997 Mar 14
68
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
24 AC CHARACTERISTICS VDD = 5 V; VSS = 0 V; Tamb = -40 to +85 C; CL = 50 pF for Port 0, ALE and PSEN; CL = 40 pF for all other outputs unless specified; tCLK = 1/ fCLK. SYMBOL Program Memory (Fig.41) tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tPXAV tAVIV tPLAZ tRLRH tWLWH tLLAX tRLDV tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ ALE pulse width address valid to ALE LOW address hold after ALE LOW ALE LOW to valid instruction in ALE LOW to PSEN LOW PSEN pulse width PSEN LOW to valid instruction in input instruction hold after PSEN input instruction float after PSEN PSEN to address valid address to valid instruction in PSEN LOW to address float 127 43 48 - 58 215 - 0 - 75 - 12 - - - 233 - - 125 - 63 - 302 - - - - 150 97 517 585 300 - 123 - - - 12 - 3tCLK - 50 4 tCLK - 40 tCLK - 60 tCLK -50 - 2tCLK - 40 tCLK - 40 tCLK - 35 - tCLK - 25 3tCLK - 35 - 0 - tCLK - 8 - 0 - - - - - - tCLK - 20 - - ns ns ns ns ns ns ns ns ns PARAMETER fosc = 12 MHz MIN. MAX. fosc = VARIABLE MIN. MAX. UNIT
4tCLK - 100 ns
3tCLK - 125 ns
5tCLK - 115 ns
External Data Memory (Figs 42 and 43) RD pulse width WR pulse width address hold after ALE LOW RD LOW to valid data in data float after RD ALE LOW to valid data in address to valid data in ALE LOW to RD or WR LOW address valid to RD or WR LOW RD or WR HIGH to ALE HIGH data valid to WR transition data valid time WR HIGH data hold after WR RD LOW to address float 400 400 48 - - - - 200 203 43 23 433 33 - 6tCLK - 100 - 6tCLK - 100 - tCLK - 35 - - - 2tCLK - 70 ns ns ns ns
5tCLK - 165 ns 8tCLK - 150 ns 9tCLK - 165 ns 3tCLK + 50 - tCLK + 40 - - 12 ns ns ns ns ns ns ns
7tCLK - 150 -
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69
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
t CY t LHLL ALE t LLPL t PLPH PSEN t LLAX t AVLL PORT 0 A0 to A7 t PLAZ t AVIV PORT 2 address A8 to A15 t PLIV inst. input t PXIX t PXAV t PXIZ t LLIV
P80CL580; P83CL580
handbook, full pagewidth
A0 to A7
inst. input
address A8 to A15
MGD680
Fig.41 Read from Program Memory.
handbook, full pagewidth
t CY t LHLL t LLDV t WHLH
ALE
PSEN t LLWL RD t AVLL t LLAX t AVWL PORT 0 A0 to A7 t RLAZ tAVDV PORT 2 address A8 to A15 (DPH) or Port 2
MGA177
t RLRH
t RHDZ t RLDV t RHDX data input
Fig.42 Read from Data Memory.
1997 Mar 14
70
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
handbook, full pagewidth
t CY t LHLL t WHLH
ALE
PSEN t LLWL t WLWH
WR t AVWL t AVLL t LLAX t QVWX PORT 0 A0 to A7 data output t QVWH t WHQX
PORT 2
address A8 to A15 (DPH) or Port 2
MGA178
Fig.43 Write to Data Memory.
1997 Mar 14
71
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
handbook, full pagewidth
one machine cycle S1 P1 P2 S2 P1 P2 S3 P1 P2 S4 P1 P2 S5 P1 P2 S6 P1 P2 S1 P1 P2 S2 P1 P2
one machine cycle S3 P1 P2 S4 P1 P2 S5 P1 P2 S6 P1 P2
dotted lines are valid when RD or WR are active
XTAL1 INPUT
ALE
only active during a read from external data memory only active during a write to external data memory
PSEN
RD
WR
external program memory fetch
BUS (PORT 0)
inst. in
address A0 - A7
inst. in
address A0 - A7
inst. in
address A0 - A7
inst. in
address A0 - A7
PORT 2
address A8 - A15
address A8 - A15
address A8 - A15
address A8 - A15
read or write of external data memory
BUS (PORT 0)
inst. in
address A0 - A7
inst. in
address A0 - A7
data output or data input
address A0 - A7
PORT 2
address A8 - A15
address A8 - A15 or Port 2 output
address A8 - A15
PORT 0, 2, 3 OUTPUT
old data
new data
PORT 1 OUTPUT
old data
new data
PORT 0, 2, 3 INPUT
sampling time of I/O port pins during input
SERIAL PORT SHIFT CLOCK (MODE 0)
MGD681
Fig.44 Instruction cycle timing.
1997 Mar 14
72
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
handbook, halfpage
0.7 VDD
0.7 VDD
0.9 V DD test points 0.4 VDD 0.3 VDD 0.3 VDD
MLA586
Fig.45 AC testing input waveform.
handbook, 4 columns
-500 A
IIL(T)
MGD682
IL
-100 A
IIL 0.5 VDD VDD
Fig.46 Input current.
1997 Mar 14
73
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
25 PACKAGE OUTLINES VSO56: plastic very small outline package; 56 leads
P80CL580; P83CL580
SOT190-1
D
E
A X
c y HE vM A
Z 56 29
Q A2 A1 pin 1 index Lp L 1 e bp 28 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 3.3 0.13 A1 0.3 0.1 0.012 0.004 A2 3.0 2.8 0.12 0.11 A3 0.25 0.01 bp 0.42 0.30 c 0.22 0.14 D (1) 21.65 21.35 E (2) 11.1 11.0 0.44 0.43 e 0.75 0.03 HE 15.8 15.2 0.62 0.60 L 2.25 0.089 Lp 1.6 1.4 0.063 0.055 Q 1.45 1.30 v 0.2 w 0.1 y 0.1 Z (1) 0.90 0.55
0.017 0.0087 0.85 0.012 0.0055 0.84
0.057 0.035 0.008 0.004 0.004 0.051 0.022
7 0o
o
Note 1. Plastic or metal protrusions of 0.3 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT190-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 96-04-02
1997 Mar 14
74
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
P80CL580; P83CL580
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT319-2
c
y X
51 52
33 32 ZE
A
e E HE A A2 A1
Q (A 3) Lp L detail X
pin 1 index
wM bp
64 1 wM D HD ZD 19
20
e
bp
vMA B vM B
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.4 1.2 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o
o
ISSUE DATE 92-11-17 95-02-04
1997 Mar 14
75
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
26 SOLDERING 26.1 Introduction
P80CL580; P83CL580
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). 26.3.2 VSO
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 26.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP and VSO packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Manual" (order code 9398 510 63011). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 26.3 26.3.1 Wave soldering QFP
Wave soldering techniques can be used for all VSO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. 26.3.3 METHOD (QFP AND VSO)
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 26.4 Repairing soldered joints
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
27 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
P80CL580; P83CL580
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 28 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 29 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Mar 14
77
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
NOTES
P80CL580; P83CL580
1997 Mar 14
78
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
NOTES
P80CL580; P83CL580
1997 Mar 14
79
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2870, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
457047/1200/04/pp80
Date of release: 1997 Mar 14
Document order number:
9397 750 01509

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